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e0c67ae1fd42708d47f8b72b31a7d173a05a4fd5
[riscv-isa-sim.git]
/
riscv
/
insns
/
mfpcr.h
1
require_supervisor
;
2
3
reg_t val
;
4
5
switch
(
insn
.
rtype
.
rs2
)
6
{
7
case
0
:
8
val
=
sr
;
9
break
;
10
case
1
:
11
val
=
epc
;
12
break
;
13
case
2
:
14
val
=
badvaddr
;
15
break
;
16
case
3
:
17
val
=
evec
;
18
break
;
19
case
4
:
20
val
=
count
;
21
break
;
22
case
5
:
23
val
=
compare
;
24
break
;
25
case
6
:
26
val
=
cause
;
27
break
;
28
case
7
:
29
val
=
0
;
30
cause
&= ~(
1
<< (
IPI_IRQ
+
CAUSE_IP_SHIFT
));
31
break
;
32
33
case
8
:
34
val
=
mmu
.
memsz
>>
PGSHIFT
;
35
break
;
36
37
case
9
:
38
val
=
mmu
.
get_ptbr
();
39
break
;
40
41
case
10
:
42
val
=
id
;
43
break
;
44
45
case
11
:
46
val
=
vecbanks
;
47
break
;
48
49
case
12
:
50
val
=
sim
->
num_cores
();
51
break
;
52
53
case
17
:
54
fromhost
=
val
=
sim
->
get_fromhost
();
55
break
;
56
57
case
24
:
58
val
=
pcr_k0
;
59
break
;
60
case
25
:
61
val
=
pcr_k1
;
62
break
;
63
64
default
:
65
val
= -
1
;
66
}
67
68
RD
=
sext_xprlen
(
val
);