ac82a56f4179219a30354d11a9e4531ee45569d4
[riscv-isa-sim.git] / riscv / insns / rem.h
1 if(RS2 == 0)
2 RD = RS1;
3 else if(sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1)
4 RD = 0;
5 else
6 RD = sext_xprlen(sext_xprlen(RS1) % sext_xprlen(RS2));