d074f26f6b5944486a2fd977f73ec999d03dcbce
[riscv-isa-sim.git] / riscv / insns / rem.h
1 sreg_t lhs = sext_xlen(RS1);
2 sreg_t rhs = sext_xlen(RS2);
3 if(rhs == 0)
4 WRITE_RD(lhs);
5 else if(lhs == INT64_MIN && rhs == -1)
6 WRITE_RD(0);
7 else
8 WRITE_RD(sext_xlen(lhs % rhs));