8234af382726a3ae1523de563637902e586d212f
[riscv-isa-sim.git] / riscv / insns / remuw.h
1 require_xpr64;
2 if(RS2 == 0)
3 RD = RS1;
4 else
5 RD = sext32(zext_xprlen(RS1) % zext_xprlen(RS2));