2bae1a864683a96b1988caa80a49419c79dda5e4
[riscv-isa-sim.git] / riscv / insns / remw.h
1 require_rv64;
2 sreg_t lhs = sext32(RS1);
3 sreg_t rhs = sext32(RS2);
4 if(rhs == 0)
5 WRITE_RD(lhs);
6 else
7 WRITE_RD(sext32(lhs % rhs));