01a45ce9094af383e151d039863e8de6df42d9e3
[riscv-isa-sim.git] / riscv / insns / sc_d.h
1 require_extension('A');
2 require_rv64;
3 if (RS1 == p->get_state()->load_reservation)
4 {
5 MMU.store_uint64(RS1, RS2);
6 WRITE_RD(0);
7 }
8 else
9 WRITE_RD(1);