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729973d478c12486da0c6f3271c2c4da9abd2042
[riscv-isa-sim.git]
/
riscv
/
insns
/
sc_w.h
1
if
(
RS1
==
p
->
get_state
()->
load_reservation
)
2
{
3
MMU
.
store_uint32
(
RS1
,
RS2
);
4
WRITE_RD
(
0
);
5
}
6
else
7
WRITE_RD
(
1
);