a933e4d2fa87fc1b5d09030b9ac23fe5b5833ba8
[riscv-isa-sim.git] / riscv / insns / scall.h
1 switch (STATE.prv)
2 {
3 case PRV_U: throw trap_user_ecall();
4 case PRV_S: throw trap_supervisor_ecall();
5 case PRV_H: throw trap_hypervisor_ecall();
6 case PRV_M: throw trap_machine_ecall();
7 }