bfaf4307df06497c9ed10b455f4cc8398772c031
[riscv-isa-sim.git] / riscv / insns / slli.h
1 if(xpr64)
2 RD = RS1 << SHAMT;
3 else
4 {
5 if(SHAMT & 0x20)
6 throw trap_illegal_instruction;
7 RD = sext32(RS1 << SHAMT);
8 }