f317d14f13e1e91c7afca59b25ff9d06db5a1cef
[riscv-isa-sim.git] / riscv / insns / sret.h
1 require_privilege(PRV_S);
2 switch (STATE.prv)
3 {
4 case PRV_S: set_pc_and_serialize(p->get_state()->sepc); break;
5 case PRV_M: set_pc_and_serialize(p->get_state()->mepc); break;
6 default: abort();
7 }
8
9 reg_t s = STATE.mstatus;
10 reg_t pie = get_field(s, MSTATUS_UPIE << STATE.prv);
11 reg_t prev_prv = get_field(s, STATE.prv == PRV_S ? MSTATUS_SPP : MSTATUS_MPP);
12 s = set_field(s, MSTATUS_UIE << prev_prv, pie); // [[prv]PP]IE = [prv]PIE
13 s = set_field(s, MSTATUS_UPIE << STATE.prv, 0); // [prv]PIE <- 0
14 s = set_field(s, STATE.prv == PRV_S ? MSTATUS_SPP : MSTATUS_MPP, PRV_U); // [prv]PP = U
15 p->set_privilege(prev_prv); // prv <- [prv]PP
16 p->set_csr(CSR_MSTATUS, s);