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8230d2724b9c1d480c20a38c90dba7cbc7372249
[riscv-isa-sim.git]
/
riscv
/
insns
/
srl.h
1
if
(
xpr64
)
2
RD
=
RS1
>> (
RS2
&
0x3F
);
3
else
4
RD
=
sext32
((
uint32_t
)
RS1
>> (
RS2
&
0x1F
));