riscv/interactive.cc

   1 // See LICENSE for license details.
   2
   3 #include "decode.h"
   4 #include "disasm.h"
   5 #include "sim.h"
   6 #include "mmu.h"
   7 #include <sys/mman.h>
   8 #include <termios.h>
   9 #include <map>
  10 #include <iostream>
  11 #include <climits>
  12 #include <cinttypes>
  13 #include <assert.h>
  14 #include <stdlib.h>
  15 #include <unistd.h>
  16 #include <sstream>
  17 #include <string>
  18 #include <vector>
  19 #include <algorithm>
  20
  21 DECLARE_TRAP(-1, interactive)
  22
  23 processor_t *sim_t::get_core(const std::string& i)
  24 {
  25   char *ptr;
  26   unsigned long p = strtoul(i.c_str(), &ptr, 10);
  27   if (*ptr || p >= procs.size())
  28     throw trap_interactive();
  29   return get_core(p);
  30 }
  31
  32 static std::string readline(int fd)
  33 {
  34   struct termios tios;
  35   bool noncanonical = tcgetattr(fd, &tios) == 0 && (tios.c_lflag & ICANON) == 0;
  36
  37   std::string s;
  38   for (char ch; read(fd, &ch, 1) == 1; )
  39   {
  40     if (ch == '\x7f')
  41     {
  42       if (s.empty())
  43         continue;
  44       s.erase(s.end()-1);
  45
  46       if (noncanonical && write(fd, "\b \b", 3) != 3)
  47         ; // shut up gcc
  48     }
  49     else if (noncanonical && write(fd, &ch, 1) != 1)
  50       ; // shut up gcc
  51
  52     if (ch == '\n')
  53       break;
  54     if (ch != '\x7f')
  55       s += ch;
  56   }
  57   return s;
  58 }
  59
  60 void sim_t::interactive()
  61 {
  62   typedef void (sim_t::*interactive_func)(const std::string&, const std::vector<std::string>&);
  63   std::map<std::string,interactive_func> funcs;
  64
  65   funcs["run"] = &sim_t::interactive_run_noisy;
  66   funcs["r"] = funcs["run"];
  67   funcs["rs"] = &sim_t::interactive_run_silent;
  68   funcs["reg"] = &sim_t::interactive_reg;
  69   funcs["fregs"] = &sim_t::interactive_fregs;
  70   funcs["fregd"] = &sim_t::interactive_fregd;
  71   funcs["pc"] = &sim_t::interactive_pc;
  72   funcs["mem"] = &sim_t::interactive_mem;
  73   funcs["str"] = &sim_t::interactive_str;
  74   funcs["until"] = &sim_t::interactive_until;
  75   funcs["while"] = &sim_t::interactive_until;
  76   funcs["quit"] = &sim_t::interactive_quit;
  77   funcs["q"] = funcs["quit"];
  78   funcs["help"] = &sim_t::interactive_help;
  79   funcs["h"] = funcs["help"];
  80
  81   while (!done())
  82   {
  83     std::cerr << ": " << std::flush;
  84     std::string s = readline(2);
  85
  86     std::stringstream ss(s);
  87     std::string cmd, tmp;
  88     std::vector<std::string> args;
  89
  90     if (!(ss >> cmd))
  91     {
  92       set_procs_debug(true);
  93       step(1);
  94       continue;
  95     }
  96
  97     while (ss >> tmp)
  98       args.push_back(tmp);
  99
 100     try
 101     {
 102       if(funcs.count(cmd))
 103         (this->*funcs[cmd])(cmd, args);
 104       else
 105         fprintf(stderr, "Unknown command %s\n", cmd.c_str());
 106     }
 107     catch(trap_t t) {}
 108   }
 109   ctrlc_pressed = false;
 110 }
 111
 112 void sim_t::interactive_help(const std::string& cmd, const std::vector<std::string>& args)
 113 {
 114   std::cerr <<
 115     "Interactive commands:\n"
 116     "reg <core> [reg]                # Display [reg] (all if omitted) in <core>\n"
 117     "fregs <core> <reg>              # Display single precision <reg> in <core>\n"
 118     "fregd <core> <reg>              # Display double precision <reg> in <core>\n"
 119     "pc <core>                       # Show current PC in <core>\n"
 120     "mem <hex addr>                  # Show contents of physical memory\n"
 121     "str <hex addr>                  # Show NUL-terminated C string\n"
 122     "until reg <core> <reg> <val>    # Stop when <reg> in <core> hits <val>\n"
 123     "until pc <core> <val>           # Stop when PC in <core> hits <val>\n"
 124     "until mem <addr> <val>          # Stop when memory <addr> becomes <val>\n"
 125     "while reg <core> <reg> <val>    # Run while <reg> in <core> is <val>\n"
 126     "while pc <core> <val>           # Run while PC in <core> is <val>\n"
 127     "while mem <addr> <val>          # Run while memory <addr> is <val>\n"
 128     "run [count]                     # Resume noisy execution (until CTRL+C, or [count] insns)\n"
 129     "r [count]                         Alias for run\n"
 130     "rs [count]                      # Resume silent execution (until CTRL+C, or [count] insns)\n"
 131     "quit                            # End the simulation\n"
 132     "q                                 Alias for quit\n"
 133     "help                            # This screen!\n"
 134     "h                                 Alias for help\n"
 135     "Note: Hitting enter is the same as: run 1\n"
 136     << std::flush;
 137 }
 138
 139 void sim_t::interactive_run_noisy(const std::string& cmd, const std::vector<std::string>& args)
 140 {
 141   interactive_run(cmd,args,true);
 142 }
 143
 144 void sim_t::interactive_run_silent(const std::string& cmd, const std::vector<std::string>& args)
 145 {
 146   interactive_run(cmd,args,false);
 147 }
 148
 149 void sim_t::interactive_run(const std::string& cmd, const std::vector<std::string>& args, bool noisy)
 150 {
 151   size_t steps = args.size() ? atoll(args[0].c_str()) : -1;
 152   ctrlc_pressed = false;
 153   set_procs_debug(noisy);
 154   for (size_t i = 0; i < steps && !ctrlc_pressed && !done(); i++)
 155     step(1);
 156 }
 157
 158 void sim_t::interactive_quit(const std::string& cmd, const std::vector<std::string>& args)
 159 {
 160   exit(0);
 161 }
 162
 163 reg_t sim_t::get_pc(const std::vector<std::string>& args)
 164 {
 165   if(args.size() != 1)
 166     throw trap_interactive();
 167
 168   processor_t *p = get_core(args[0]);
 169   return p->state.pc;
 170 }
 171
 172 void sim_t::interactive_pc(const std::string& cmd, const std::vector<std::string>& args)
 173 {
 174   fprintf(stderr, "0x%016" PRIx64 "\n", get_pc(args));
 175 }
 176
 177 reg_t sim_t::get_reg(const std::vector<std::string>& args)
 178 {
 179   if(args.size() != 2)
 180     throw trap_interactive();
 181
 182   processor_t *p = get_core(args[0]);
 183
 184   unsigned long r = std::find(xpr_name, xpr_name + NXPR, args[1]) - xpr_name;
 185   if (r == NXPR) {
 186     char *ptr;
 187     r = strtoul(args[1].c_str(), &ptr, 10);
 188     if (*ptr) {
 189       #define DECLARE_CSR(name, number) if (args[1] == #name) return p->get_csr(number);
 190       #include "encoding.h"              // generates if's for all csrs
 191       r = NXPR;                          // else case (csr name not found)
 192       #undef DECLARE_CSR
 193     }
 194   }
 195
 196   if (r >= NXPR)
 197     throw trap_interactive();
 198
 199   return p->state.XPR[r];
 200 }
 201
 202 reg_t sim_t::get_freg(const std::vector<std::string>& args)
 203 {
 204   if(args.size() != 2)
 205     throw trap_interactive();
 206
 207   processor_t *p = get_core(args[0]);
 208   int r = std::find(fpr_name, fpr_name + NFPR, args[1]) - fpr_name;
 209   if (r == NFPR)
 210     r = atoi(args[1].c_str());
 211   if (r >= NFPR)
 212     throw trap_interactive();
 213
 214   return p->state.FPR[r];
 215 }
 216
 217 void sim_t::interactive_reg(const std::string& cmd, const std::vector<std::string>& args)
 218 {
 219   if (args.size() == 1) {
 220     // Show all the regs!
 221     processor_t *p = get_core(args[0]);
 222
 223     for (int r = 0; r < NXPR; ++r) {
 224       fprintf(stderr, "%-4s: 0x%016" PRIx64 "  ", xpr_name[r], p->state.XPR[r]);
 225       if ((r + 1) % 4 == 0)
 226         fprintf(stderr, "\n");
 227     }
 228   } else
 229     fprintf(stderr, "0x%016" PRIx64 "\n", get_reg(args));
 230 }
 231
 232 union fpr
 233 {
 234   reg_t r;
 235   float s;
 236   double d;
 237 };
 238
 239 void sim_t::interactive_fregs(const std::string& cmd, const std::vector<std::string>& args)
 240 {
 241   fpr f;
 242   f.r = get_freg(args);
 243   fprintf(stderr, "%g\n",f.s);
 244 }
 245
 246 void sim_t::interactive_fregd(const std::string& cmd, const std::vector<std::string>& args)
 247 {
 248   fpr f;
 249   f.r = get_freg(args);
 250   fprintf(stderr, "%g\n",f.d);
 251 }
 252
 253 reg_t sim_t::get_mem(const std::vector<std::string>& args)
 254 {
 255   if(args.size() != 1 && args.size() != 2)
 256     throw trap_interactive();
 257
 258   std::string addr_str = args[0];
 259   mmu_t* mmu = debug_mmu;
 260   if(args.size() == 2)
 261   {
 262     processor_t *p = get_core(args[0]);
 263     mmu = p->get_mmu();
 264     addr_str = args[1];
 265   }
 266
 267   reg_t addr = strtol(addr_str.c_str(),NULL,16), val;
 268   if(addr == LONG_MAX)
 269     addr = strtoul(addr_str.c_str(),NULL,16);
 270
 271   switch(addr % 8)
 272   {
 273     case 0:
 274       val = mmu->load_uint64(addr);
 275       break;
 276     case 4:
 277       val = mmu->load_uint32(addr);
 278       break;
 279     case 2:
 280     case 6:
 281       val = mmu->load_uint16(addr);
 282       break;
 283     default:
 284       val = mmu->load_uint8(addr);
 285       break;
 286   }
 287   return val;
 288 }
 289
 290 void sim_t::interactive_mem(const std::string& cmd, const std::vector<std::string>& args)
 291 {
 292   fprintf(stderr, "0x%016" PRIx64 "\n", get_mem(args));
 293 }
 294
 295 void sim_t::interactive_str(const std::string& cmd, const std::vector<std::string>& args)
 296 {
 297   if(args.size() != 1)
 298     throw trap_interactive();
 299
 300   reg_t addr = strtol(args[0].c_str(),NULL,16);
 301
 302   char ch;
 303   while((ch = debug_mmu->load_uint8(addr++)))
 304     putchar(ch);
 305
 306   putchar('\n');
 307 }
 308
 309 void sim_t::interactive_until(const std::string& cmd, const std::vector<std::string>& args)
 310 {
 311   bool cmd_until = cmd == "until";
 312
 313   if(args.size() < 3)
 314     return;
 315
 316   reg_t val = strtol(args[args.size()-1].c_str(),NULL,16);
 317   if(val == LONG_MAX)
 318     val = strtoul(args[args.size()-1].c_str(),NULL,16);
 319
 320   std::vector<std::string> args2;
 321   args2 = std::vector<std::string>(args.begin()+1,args.end()-1);
 322
 323   auto func = args[0] == "reg" ? &sim_t::get_reg :
 324               args[0] == "pc"  ? &sim_t::get_pc :
 325               args[0] == "mem" ? &sim_t::get_mem :
 326               NULL;
 327
 328   if (func == NULL)
 329     return;
 330
 331   ctrlc_pressed = false;
 332
 333   while (1)
 334   {
 335     try
 336     {
 337       reg_t current = (this->*func)(args2);
 338
 339       if (cmd_until == (current == val))
 340         break;
 341       if (ctrlc_pressed)
 342         break;
 343     }
 344     catch (trap_t t) {}
 345
 346     set_procs_debug(false);
 347     step(1);
 348   }
 349 }