e425c8e976cbb51858339b61f779c304e2e06577
[riscv-isa-sim.git] / riscv / jtag_dtm.h
1 #ifndef JTAG_DTM_H
2 #define JTAG_DTM_H
3
4 #include <stdint.h>
5
6 typedef enum {
7 TEST_LOGIC_RESET,
8 RUN_TEST_IDLE,
9 SELECT_DR_SCAN,
10 CAPTURE_DR,
11 SHIFT_DR,
12 EXIT1_DR,
13 PAUSE_DR,
14 EXIT2_DR,
15 UPDATE_DR,
16 SELECT_IR_SCAN,
17 CAPTURE_IR,
18 SHIFT_IR,
19 EXIT1_IR,
20 PAUSE_IR,
21 EXIT2_IR,
22 UPDATE_IR
23 } jtag_state_t;
24
25 class jtag_dtm_t
26 {
27 static const unsigned idcode_ir = 1;
28 static const unsigned idcode_dr = 0xdeadbeef;
29 static const unsigned dtmcontrol_ir = 0x10;
30
31 public:
32 jtag_dtm_t() :
33 dtmcontrol(
34 (6 << 4) | // abits
35 1 // version
36 ),
37 state(TEST_LOGIC_RESET) {}
38
39 void reset() {
40 state = TEST_LOGIC_RESET;
41 }
42
43 void set_pins(bool tck, bool tms, bool tdi);
44
45 bool tdo() const { return _tdo; }
46
47 private:
48 bool _tck, _tms, _tdi, _tdo;
49 uint32_t ir;
50 const unsigned ir_length = 5;
51 uint64_t dr;
52 unsigned dr_length;
53
54 uint32_t dtmcontrol;
55
56 jtag_state_t state;
57
58 void capture_dr();
59 void update_dr();
60
61 const jtag_state_t next[16][2] = {
62 /* TEST_LOGIC_RESET */ { RUN_TEST_IDLE, TEST_LOGIC_RESET },
63 /* RUN_TEST_IDLE */ { RUN_TEST_IDLE, SELECT_DR_SCAN },
64 /* SELECT_DR_SCAN */ { CAPTURE_DR, SELECT_IR_SCAN },
65 /* CAPTURE_DR */ { SHIFT_DR, EXIT1_DR },
66 /* SHIFT_DR */ { SHIFT_DR, EXIT1_DR },
67 /* EXIT1_DR */ { PAUSE_DR, UPDATE_DR },
68 /* PAUSE_DR */ { PAUSE_DR, EXIT2_DR },
69 /* EXIT2_DR */ { SHIFT_DR, UPDATE_DR },
70 /* UPDATE_DR */ { RUN_TEST_IDLE, SELECT_DR_SCAN },
71 /* SELECT_IR_SCAN */ { CAPTURE_IR, TEST_LOGIC_RESET },
72 /* CAPTURE_IR */ { SHIFT_IR, EXIT1_IR },
73 /* SHIFT_IR */ { SHIFT_IR, EXIT1_IR },
74 /* EXIT1_IR */ { PAUSE_IR, UPDATE_IR },
75 /* PAUSE_IR */ { PAUSE_IR, EXIT2_IR },
76 /* EXIT2_IR */ { SHIFT_IR, UPDATE_IR },
77 /* UPDATE_IR */ { RUN_TEST_IDLE, SELECT_DR_SCAN }
78 };
79 };
80
81 #endif