riscv/mmu.cc

   1 // See LICENSE for license details.
   2
   3 #include "mmu.h"
   4 #include "sim.h"
   5 #include "processor.h"
   6
   7 mmu_t::mmu_t(char* _mem, size_t _memsz)
   8  : mem(_mem), memsz(_memsz), proc(NULL)
   9 {
  10   flush_tlb();
  11 }
  12
  13 mmu_t::~mmu_t()
  14 {
  15 }
  16
  17 void mmu_t::flush_icache()
  18 {
  19   for (size_t i = 0; i < ICACHE_ENTRIES; i++)
  20     icache[i].tag = -1;
  21 }
  22
  23 void mmu_t::flush_tlb()
  24 {
  25   memset(tlb_insn_tag, -1, sizeof(tlb_insn_tag));
  26   memset(tlb_load_tag, -1, sizeof(tlb_load_tag));
  27   memset(tlb_store_tag, -1, sizeof(tlb_store_tag));
  28
  29   flush_icache();
  30 }
  31
  32 reg_t mmu_t::translate(reg_t addr, access_type type)
  33 {
  34   if (!proc)
  35     return addr;
  36
  37   reg_t mode = proc->state.prv;
  38   bool pum = false;
  39   if (type != FETCH) {
  40     if (get_field(proc->state.mstatus, MSTATUS_MPRV))
  41       mode = get_field(proc->state.mstatus, MSTATUS_MPP);
  42     pum = (mode == PRV_S && get_field(proc->state.mstatus, MSTATUS_PUM));
  43   }
  44   if (get_field(proc->state.mstatus, MSTATUS_VM) == VM_MBARE)
  45     mode = PRV_M;
  46
  47   if (mode == PRV_M) {
  48     reg_t msb_mask = (reg_t(2) << (proc->xlen-1))-1; // zero-extend from xlen
  49     return addr & msb_mask;
  50   }
  51   return walk(addr, type, mode > PRV_U, pum) | (addr & (PGSIZE-1));
  52 }
  53
  54 const uint16_t* mmu_t::fetch_slow_path(reg_t addr)
  55 {
  56   reg_t paddr = translate(addr, FETCH);
  57   if (paddr < memsz)
  58     refill_tlb(addr, paddr, FETCH);
  59   else
  60     throw trap_instruction_access_fault(addr);
  61   return (const uint16_t*)(mem + paddr);
  62 }
  63
  64 void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes)
  65 {
  66   reg_t paddr = translate(addr, LOAD);
  67   if (paddr < memsz) {
  68     memcpy(bytes, mem + paddr, len);
  69     if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD))
  70       tracer.trace(paddr, len, LOAD);
  71     else
  72       refill_tlb(addr, paddr, LOAD);
  73   } else if (!proc || !proc->sim->mmio_load(paddr, len, bytes)) {
  74     throw trap_load_access_fault(addr);
  75   }
  76 }
  77
  78 void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes)
  79 {
  80   reg_t paddr = translate(addr, STORE);
  81   if (paddr < memsz) {
  82     memcpy(mem + paddr, bytes, len);
  83     if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE))
  84       tracer.trace(paddr, len, STORE);
  85     else
  86       refill_tlb(addr, paddr, STORE);
  87   } else if (!proc || !proc->sim->mmio_store(paddr, len, bytes)) {
  88     throw trap_store_access_fault(addr);
  89   }
  90 }
  91
  92 void mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, access_type type)
  93 {
  94   reg_t idx = (vaddr >> PGSHIFT) % TLB_ENTRIES;
  95   reg_t expected_tag = vaddr >> PGSHIFT;
  96
  97   if (tlb_load_tag[idx] != expected_tag) tlb_load_tag[idx] = -1;
  98   if (tlb_store_tag[idx] != expected_tag) tlb_store_tag[idx] = -1;
  99   if (tlb_insn_tag[idx] != expected_tag) tlb_insn_tag[idx] = -1;
 100
 101   if (type == FETCH) tlb_insn_tag[idx] = expected_tag;
 102   else if (type == STORE) tlb_store_tag[idx] = expected_tag;
 103   else tlb_load_tag[idx] = expected_tag;
 104
 105   tlb_data[idx] = mem + paddr - vaddr;
 106 }
 107
 108 reg_t mmu_t::walk(reg_t addr, access_type type, bool supervisor, bool pum)
 109 {
 110   int levels, ptidxbits, ptesize;
 111   switch (get_field(proc->get_state()->mstatus, MSTATUS_VM))
 112   {
 113     case VM_SV32: levels = 2; ptidxbits = 10; ptesize = 4; break;
 114     case VM_SV39: levels = 3; ptidxbits = 9; ptesize = 8; break;
 115     case VM_SV48: levels = 4; ptidxbits = 9; ptesize = 8; break;
 116     default: abort();
 117   }
 118
 119   // verify bits xlen-1:va_bits-1 are all equal
 120   int va_bits = PGSHIFT + levels * ptidxbits;
 121   reg_t mask = (reg_t(1) << (proc->xlen - (va_bits-1))) - 1;
 122   reg_t masked_msbs = (addr >> (va_bits-1)) & mask;
 123   if (masked_msbs != 0 && masked_msbs != mask)
 124     return -1;
 125
 126   reg_t base = proc->get_state()->sptbr << PGSHIFT;
 127   int ptshift = (levels - 1) * ptidxbits;
 128   for (int i = 0; i < levels; i++, ptshift -= ptidxbits) {
 129     reg_t idx = (addr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
 130
 131     // check that physical address of PTE is legal
 132     reg_t pte_addr = base + idx * ptesize;
 133     if (pte_addr >= memsz)
 134       break;
 135
 136     void* ppte = mem + pte_addr;
 137     reg_t pte = ptesize == 4 ? *(uint32_t*)ppte : *(uint64_t*)ppte;
 138     reg_t ppn = pte >> PTE_PPN_SHIFT;
 139
 140     if (PTE_TABLE(pte)) { // next level of page table
 141       base = ppn << PGSHIFT;
 142     } else if (pum && PTE_CHECK_PERM(pte, 0, type == STORE, type == FETCH)) {
 143       break;
 144     } else if (!PTE_CHECK_PERM(pte, supervisor, type == STORE, type == FETCH)) {
 145       break;
 146     } else {
 147       // set referenced and possibly dirty bits.
 148       *(uint32_t*)ppte |= PTE_R | ((type == STORE) * PTE_D);
 149       // for superpage mappings, make a fake leaf PTE for the TLB's benefit.
 150       reg_t vpn = addr >> PGSHIFT;
 151       return (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
 152     }
 153   }
 154
 155   return -1;
 156 }
 157
 158 void mmu_t::register_memtracer(memtracer_t* t)
 159 {
 160   flush_tlb();
 161   tracer.hook(t);
 162 }