riscv/mmu.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_MMU_H
   4 #define _RISCV_MMU_H
   5
   6 #include "decode.h"
   7 #include "trap.h"
   8 #include "common.h"
   9 #include "config.h"
  10 #include "sim.h"
  11 #include "processor.h"
  12 #include "memtracer.h"
  13 #include <stdlib.h>
  14 #include <vector>
  15
  16 // virtual memory configuration
  17 #define PGSHIFT 12
  18 const reg_t PGSIZE = 1 << PGSHIFT;
  19 const reg_t PGMASK = ~(PGSIZE-1);
  20
  21 struct insn_fetch_t
  22 {
  23   insn_func_t func;
  24   insn_t insn;
  25 };
  26
  27 struct icache_entry_t {
  28   reg_t tag;
  29   reg_t pad;
  30   insn_fetch_t data;
  31 };
  32
  33 class trigger_matched_t
  34 {
  35   public:
  36     trigger_matched_t(int index,
  37         trigger_operation_t operation, reg_t address, reg_t data) :
  38       index(index), operation(operation), address(address), data(data) {}
  39
  40     int index;
  41     trigger_operation_t operation;
  42     reg_t address;
  43     reg_t data;
  44 };
  45
  46 // this class implements a processor's port into the virtual memory system.
  47 // an MMU and instruction cache are maintained for simulator performance.
  48 class mmu_t
  49 {
  50 public:
  51   mmu_t(sim_t* sim, processor_t* proc);
  52   ~mmu_t();
  53
  54   // template for functions that load an aligned value from memory
  55   #define load_func(type) \
  56     inline type##_t load_##type(reg_t addr) { \
  57       if (addr & (sizeof(type##_t)-1)) \
  58         throw trap_load_address_misaligned(addr); \
  59       reg_t vpn = addr >> PGSHIFT; \
  60       if (likely(tlb_load_tag[vpn % TLB_ENTRIES] == vpn)) \
  61         return *(type##_t*)(tlb_data[vpn % TLB_ENTRIES] + addr); \
  62       if (unlikely(tlb_load_tag[vpn % TLB_ENTRIES] == (vpn | TLB_CHECK_TRIGGERS))) { \
  63         type##_t data = *(type##_t*)(tlb_data[vpn % TLB_ENTRIES] + addr); \
  64         if (!matched_trigger) { \
  65           matched_trigger = trigger_exception(OPERATION_LOAD, addr, data); \
  66           if (matched_trigger) \
  67             throw *matched_trigger; \
  68         } \
  69         return data; \
  70       } \
  71       type##_t res; \
  72       load_slow_path(addr, sizeof(type##_t), (uint8_t*)&res); \
  73       return res; \
  74     }
  75
  76   // load value from memory at aligned address; zero extend to register width
  77   load_func(uint8)
  78   load_func(uint16)
  79   load_func(uint32)
  80   load_func(uint64)
  81
  82   // load value from memory at aligned address; sign extend to register width
  83   load_func(int8)
  84   load_func(int16)
  85   load_func(int32)
  86   load_func(int64)
  87
  88   // template for functions that store an aligned value to memory
  89   #define store_func(type) \
  90     void store_##type(reg_t addr, type##_t val) { \
  91       if (addr & (sizeof(type##_t)-1)) \
  92         throw trap_store_address_misaligned(addr); \
  93       reg_t vpn = addr >> PGSHIFT; \
  94       if (likely(tlb_store_tag[vpn % TLB_ENTRIES] == vpn)) \
  95         *(type##_t*)(tlb_data[vpn % TLB_ENTRIES] + addr) = val; \
  96       else if (unlikely(tlb_store_tag[vpn % TLB_ENTRIES] == (vpn | TLB_CHECK_TRIGGERS))) { \
  97         if (!matched_trigger) { \
  98           matched_trigger = trigger_exception(OPERATION_STORE, addr, val); \
  99           if (matched_trigger) \
 100             throw *matched_trigger; \
 101         } \
 102         *(type##_t*)(tlb_data[vpn % TLB_ENTRIES] + addr) = val; \
 103       } \
 104       else \
 105         store_slow_path(addr, sizeof(type##_t), (const uint8_t*)&val); \
 106     }
 107
 108   // template for functions that perform an atomic memory operation
 109   #define amo_func(type) \
 110     template<typename op> \
 111     type##_t amo_##type(reg_t addr, op f) { \
 112       if (addr & (sizeof(type##_t)-1)) \
 113         throw trap_store_address_misaligned(addr); \
 114       try { \
 115         auto lhs = load_##type(addr); \
 116         store_##type(addr, f(lhs)); \
 117         return lhs; \
 118       } catch (trap_load_access_fault& t) { \
 119         /* AMO faults should be reported as store faults */ \
 120         throw trap_store_access_fault(t.get_badaddr()); \
 121       } \
 122     }
 123
 124   // store value to memory at aligned address
 125   store_func(uint8)
 126   store_func(uint16)
 127   store_func(uint32)
 128   store_func(uint64)
 129
 130   // perform an atomic memory operation at an aligned address
 131   amo_func(uint32)
 132   amo_func(uint64)
 133
 134   static const reg_t ICACHE_ENTRIES = 1024;
 135
 136   inline size_t icache_index(reg_t addr)
 137   {
 138     return (addr / PC_ALIGN) % ICACHE_ENTRIES;
 139   }
 140
 141   inline icache_entry_t* refill_icache(reg_t addr, icache_entry_t* entry)
 142   {
 143     const uint16_t* iaddr = translate_insn_addr(addr);
 144     insn_bits_t insn = *iaddr;
 145     int length = insn_length(insn);
 146
 147     if (likely(length == 4)) {
 148       insn |= (insn_bits_t)*(const int16_t*)translate_insn_addr(addr + 2) << 16;
 149     } else if (length == 2) {
 150       insn = (int16_t)insn;
 151     } else if (length == 6) {
 152       insn |= (insn_bits_t)*(const int16_t*)translate_insn_addr(addr + 4) << 32;
 153       insn |= (insn_bits_t)*(const uint16_t*)translate_insn_addr(addr + 2) << 16;
 154     } else {
 155       static_assert(sizeof(insn_bits_t) == 8, "insn_bits_t must be uint64_t");
 156       insn |= (insn_bits_t)*(const int16_t*)translate_insn_addr(addr + 6) << 48;
 157       insn |= (insn_bits_t)*(const uint16_t*)translate_insn_addr(addr + 4) << 32;
 158       insn |= (insn_bits_t)*(const uint16_t*)translate_insn_addr(addr + 2) << 16;
 159     }
 160
 161     insn_fetch_t fetch = {proc->decode_insn(insn), insn};
 162     entry->tag = addr;
 163     entry->data = fetch;
 164
 165     reg_t paddr = sim->mem_to_addr((char*)iaddr);
 166     if (tracer.interested_in_range(paddr, paddr + 1, FETCH)) {
 167       entry->tag = -1;
 168       tracer.trace(paddr, length, FETCH);
 169     }
 170     return entry;
 171   }
 172
 173   inline icache_entry_t* access_icache(reg_t addr)
 174   {
 175     icache_entry_t* entry = &icache[icache_index(addr)];
 176     if (likely(entry->tag == addr))
 177       return entry;
 178     return refill_icache(addr, entry);
 179   }
 180
 181   inline insn_fetch_t load_insn(reg_t addr)
 182   {
 183     icache_entry_t entry;
 184     return refill_icache(addr, &entry)->data;
 185   }
 186
 187   void flush_tlb();
 188   void flush_icache();
 189
 190   void register_memtracer(memtracer_t*);
 191
 192 private:
 193   sim_t* sim;
 194   processor_t* proc;
 195   memtracer_list_t tracer;
 196   uint16_t fetch_temp;
 197
 198   // implement an instruction cache for simulator performance
 199   icache_entry_t icache[ICACHE_ENTRIES];
 200
 201   // implement a TLB for simulator performance
 202   static const reg_t TLB_ENTRIES = 256;
 203   // If a TLB tag has TLB_CHECK_TRIGGERS set, then the MMU must check for a
 204   // trigger match before completing an access.
 205   static const reg_t TLB_CHECK_TRIGGERS = reg_t(1) << 63;
 206   char* tlb_data[TLB_ENTRIES];
 207   reg_t tlb_insn_tag[TLB_ENTRIES];
 208   reg_t tlb_load_tag[TLB_ENTRIES];
 209   reg_t tlb_store_tag[TLB_ENTRIES];
 210
 211   // finish translation on a TLB miss and update the TLB
 212   void refill_tlb(reg_t vaddr, reg_t paddr, access_type type);
 213   const char* fill_from_mmio(reg_t vaddr, reg_t paddr);
 214
 215   // perform a page table walk for a given VA; set referenced/dirty bits
 216   reg_t walk(reg_t addr, access_type type, reg_t prv);
 217
 218   // handle uncommon cases: TLB misses, page faults, MMIO
 219   const uint16_t* fetch_slow_path(reg_t addr);
 220   void load_slow_path(reg_t addr, reg_t len, uint8_t* bytes);
 221   void store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes);
 222   reg_t translate(reg_t addr, access_type type);
 223
 224   // ITLB lookup
 225   inline const uint16_t* translate_insn_addr(reg_t addr) {
 226     reg_t vpn = addr >> PGSHIFT;
 227     if (likely(tlb_insn_tag[vpn % TLB_ENTRIES] == vpn))
 228       return (uint16_t*)(tlb_data[vpn % TLB_ENTRIES] + addr);
 229     if (unlikely(tlb_insn_tag[vpn % TLB_ENTRIES] == (vpn | TLB_CHECK_TRIGGERS))) {
 230       uint16_t* ptr = (uint16_t*)(tlb_data[vpn % TLB_ENTRIES] + addr);
 231       int match = proc->trigger_match(OPERATION_EXECUTE, addr, *ptr);
 232       if (match >= 0)
 233         throw trigger_matched_t(match, OPERATION_EXECUTE, addr, *ptr);
 234       return ptr;
 235     }
 236     return fetch_slow_path(addr);
 237   }
 238
 239   inline trigger_matched_t *trigger_exception(trigger_operation_t operation,
 240       reg_t address, reg_t data)
 241   {
 242     if (!proc) {
 243       return NULL;
 244     }
 245     int match = proc->trigger_match(operation, address, data);
 246     if (match == -1)
 247       return NULL;
 248     if (proc->state.mcontrol[match].timing == 0) {
 249       throw trigger_matched_t(match, operation, address, data);
 250     }
 251     return new trigger_matched_t(match, operation, address, data);
 252   }
 253
 254   bool check_triggers_fetch;
 255   bool check_triggers_load;
 256   bool check_triggers_store;
 257   // The exception describing a matched trigger, or NULL.
 258   trigger_matched_t *matched_trigger;
 259
 260   friend class processor_t;
 261 };
 262
 263 struct vm_info {
 264   int levels;
 265   int idxbits;
 266   int ptesize;
 267   reg_t ptbase;
 268 };
 269
 270 inline vm_info decode_vm_info(int xlen, reg_t prv, reg_t sptbr)
 271 {
 272   if (prv == PRV_M) {
 273     return {0, 0, 0, 0};
 274   } else if (prv <= PRV_S && xlen == 32) {
 275     switch (get_field(sptbr, SPTBR32_MODE)) {
 276       case SPTBR_MODE_OFF: return {0, 0, 0, 0};
 277       case SPTBR_MODE_SV32: return {2, 10, 4, (sptbr & SPTBR32_PPN) << PGSHIFT};
 278       default: abort();
 279     }
 280   } else if (prv <= PRV_S && xlen == 64) {
 281     switch (get_field(sptbr, SPTBR64_MODE)) {
 282       case SPTBR_MODE_OFF: return {0, 0, 0, 0};
 283       case SPTBR_MODE_SV39: return {3, 9, 8, (sptbr & SPTBR64_PPN) << PGSHIFT};
 284       case SPTBR_MODE_SV48: return {4, 9, 8, (sptbr & SPTBR64_PPN) << PGSHIFT};
 285       case SPTBR_MODE_SV57: return {5, 9, 8, (sptbr & SPTBR64_PPN) << PGSHIFT};
 286       case SPTBR_MODE_SV64: return {6, 9, 8, (sptbr & SPTBR64_PPN) << PGSHIFT};
 287       default: abort();
 288     }
 289   } else {
 290     abort();
 291   }
 292 }
 293
 294 #endif