riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include "gdbserver.h"
  11 #include <cinttypes>
  12 #include <cmath>
  13 #include <cstdlib>
  14 #include <iostream>
  15 #include <assert.h>
  16 #include <limits.h>
  17 #include <stdexcept>
  18 #include <algorithm>
  19
  20 #undef STATE
  21 #define STATE state
  22
  23 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  24         bool halt_on_reset)
  25   : debug(false), sim(sim), ext(NULL), id(id), halt_on_reset(halt_on_reset)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31   disassembler = new disassembler_t(max_xlen);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = all_subsets;
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87   isa |= 1L << ('u' - 'a'); // advertise support for user mode
  88
  89   while (*p) {
  90     isa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   // advertise support for supervisor and user modes
 110   isa |= 1L << ('s' - 'a');
 111   isa |= 1L << ('u' - 'a');
 112
 113   max_isa = isa;
 114 }
 115
 116 void state_t::reset()
 117 {
 118   memset(this, 0, sizeof(*this));
 119   prv = PRV_M;
 120   pc = DEFAULT_RSTVEC;
 121   mtvec = DEFAULT_MTVEC;
 122   load_reservation = -1;
 123   tselect = 0;
 124   for (unsigned int i = 0; i < num_triggers; i++)
 125     mcontrol[i].type = 2;
 126 }
 127
 128 void processor_t::set_debug(bool value)
 129 {
 130   debug = value;
 131   if (ext)
 132     ext->set_debug(value);
 133 }
 134
 135 void processor_t::set_histogram(bool value)
 136 {
 137   histogram_enabled = value;
 138 #ifndef RISCV_ENABLE_HISTOGRAM
 139   if (value) {
 140     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 141     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 142   }
 143 #endif
 144 }
 145
 146 void processor_t::reset()
 147 {
 148   state.reset();
 149   state.dcsr.halt = halt_on_reset;
 150   halt_on_reset = false;
 151   set_csr(CSR_MSTATUS, state.mstatus);
 152
 153   if (ext)
 154     ext->reset(); // reset the extension
 155 }
 156
 157 // Count number of contiguous 0 bits starting from the LSB.
 158 static int ctz(reg_t val)
 159 {
 160   int res = 0;
 161   if (val)
 162     while ((val & 1) == 0)
 163       val >>= 1, res++;
 164   return res;
 165 }
 166
 167 void processor_t::take_interrupt(reg_t pending_interrupts)
 168 {
 169   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 170   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 171   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 172
 173   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 174   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 175   if (enabled_interrupts == 0)
 176     enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
 177
 178   if (enabled_interrupts)
 179     throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
 180 }
 181
 182 void processor_t::set_privilege(reg_t prv)
 183 {
 184   assert(prv <= PRV_M);
 185   if (prv == PRV_H)
 186     prv = PRV_U;
 187   mmu->flush_tlb();
 188   state.prv = prv;
 189 }
 190
 191 void processor_t::enter_debug_mode(uint8_t cause)
 192 {
 193   state.dcsr.cause = cause;
 194   state.dcsr.prv = state.prv;
 195   set_privilege(PRV_M);
 196   state.dpc = state.pc;
 197   state.pc = DEBUG_ROM_START;
 198 }
 199
 200 void processor_t::take_trap(trap_t& t, reg_t epc)
 201 {
 202   if (debug) {
 203     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 204             id, t.name(), epc);
 205     if (t.has_badaddr())
 206       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 207           t.get_badaddr());
 208   }
 209
 210   if (t.cause() == CAUSE_BREAKPOINT && (
 211               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 212               (state.prv == PRV_H && state.dcsr.ebreakh) ||
 213               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 214               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 215     enter_debug_mode(DCSR_CAUSE_SWBP);
 216     return;
 217   }
 218
 219   if (state.dcsr.cause) {
 220     state.pc = DEBUG_ROM_EXCEPTION;
 221     return;
 222   }
 223
 224   // by default, trap to M-mode, unless delegated to S-mode
 225   reg_t bit = t.cause();
 226   reg_t deleg = state.medeleg;
 227   if (bit & ((reg_t)1 << (max_xlen-1)))
 228     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 229   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 230     // handle the trap in S-mode
 231     state.pc = state.stvec;
 232     state.scause = t.cause();
 233     state.sepc = epc;
 234     if (t.has_badaddr())
 235       state.sbadaddr = t.get_badaddr();
 236
 237     reg_t s = state.mstatus;
 238     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
 239     s = set_field(s, MSTATUS_SPP, state.prv);
 240     s = set_field(s, MSTATUS_SIE, 0);
 241     set_csr(CSR_MSTATUS, s);
 242     set_privilege(PRV_S);
 243   } else {
 244     state.pc = state.mtvec;
 245     state.mepc = epc;
 246     state.mcause = t.cause();
 247     if (t.has_badaddr())
 248       state.mbadaddr = t.get_badaddr();
 249
 250     reg_t s = state.mstatus;
 251     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
 252     s = set_field(s, MSTATUS_MPP, state.prv);
 253     s = set_field(s, MSTATUS_MIE, 0);
 254     set_csr(CSR_MSTATUS, s);
 255     set_privilege(PRV_M);
 256   }
 257
 258   yield_load_reservation();
 259 }
 260
 261 void processor_t::disasm(insn_t insn)
 262 {
 263   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 264   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 265           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 266 }
 267
 268 int processor_t::paddr_bits()
 269 {
 270   assert(xlen == max_xlen);
 271   return max_xlen == 64 ? 50 : 34;
 272 }
 273
 274 void processor_t::set_csr(int which, reg_t val)
 275 {
 276   val = zext_xlen(val);
 277   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 278   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 279   switch (which)
 280   {
 281     case CSR_FFLAGS:
 282       dirty_fp_state;
 283       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 284       break;
 285     case CSR_FRM:
 286       dirty_fp_state;
 287       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 288       break;
 289     case CSR_FCSR:
 290       dirty_fp_state;
 291       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 292       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 293       break;
 294     case CSR_MSTATUS: {
 295       if ((val ^ state.mstatus) &
 296           (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM | MSTATUS_MXR))
 297         mmu->flush_tlb();
 298
 299       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 300                  | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
 301                  | MSTATUS_MPP | MSTATUS_MXR | (ext ? MSTATUS_XS : 0);
 302
 303       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 304
 305       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 306       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 307       if (max_xlen == 32)
 308         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 309       else
 310         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 311
 312       // spike supports the notion of xlen < max_xlen, but current priv spec
 313       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 314       xlen = max_xlen;
 315       break;
 316     }
 317     case CSR_MIP: {
 318       reg_t mask = MIP_SSIP | MIP_STIP;
 319       state.mip = (state.mip & ~mask) | (val & mask);
 320       break;
 321     }
 322     case CSR_MIE:
 323       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 324       break;
 325     case CSR_MIDELEG:
 326       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 327       break;
 328     case CSR_MEDELEG: {
 329       reg_t mask = 0;
 330 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
 331 #include "encoding.h"
 332 #undef DECLARE_CAUSE
 333       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 334       break;
 335     }
 336     case CSR_MINSTRET:
 337     case CSR_MCYCLE:
 338       if (xlen == 32)
 339         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 340       else
 341         state.minstret = val;
 342       break;
 343     case CSR_MINSTRETH:
 344     case CSR_MCYCLEH:
 345       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 346       break;
 347     case CSR_MUCOUNTEREN:
 348       state.mucounteren = val;
 349       break;
 350     case CSR_MSCOUNTEREN:
 351       state.mscounteren = val;
 352       break;
 353     case CSR_SSTATUS: {
 354       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 355                  | SSTATUS_XS | SSTATUS_PUM;
 356       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 357     }
 358     case CSR_SIP: {
 359       reg_t mask = MIP_SSIP & state.mideleg;
 360       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
 361     }
 362     case CSR_SIE:
 363       return set_csr(CSR_MIE,
 364                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 365     case CSR_SPTBR: {
 366       mmu->flush_tlb();
 367       if (max_xlen == 32)
 368         state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE);
 369       if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF ||
 370                              get_field(val, SPTBR64_MODE) >= SPTBR_MODE_SV39))
 371         state.sptbr = val & (SPTBR64_PPN | SPTBR64_MODE);
 372       break;
 373     }
 374     case CSR_SEPC: state.sepc = val; break;
 375     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 376     case CSR_SSCRATCH: state.sscratch = val; break;
 377     case CSR_SCAUSE: state.scause = val; break;
 378     case CSR_SBADADDR: state.sbadaddr = val; break;
 379     case CSR_MEPC: state.mepc = val; break;
 380     case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
 381     case CSR_MSCRATCH: state.mscratch = val; break;
 382     case CSR_MCAUSE: state.mcause = val; break;
 383     case CSR_MBADADDR: state.mbadaddr = val; break;
 384     case CSR_MISA: {
 385       if (!(val & (1L << ('F' - 'A'))))
 386         val &= ~(1L << ('D' - 'A'));
 387
 388       // allow MAFDC bits in MISA to be modified
 389       reg_t mask = 0;
 390       mask |= 1L << ('M' - 'A');
 391       mask |= 1L << ('A' - 'A');
 392       mask |= 1L << ('F' - 'A');
 393       mask |= 1L << ('D' - 'A');
 394       mask |= 1L << ('C' - 'A');
 395       mask &= max_isa;
 396
 397       isa = (val & mask) | (isa & ~mask);
 398       break;
 399     }
 400     case CSR_TSELECT:
 401       if (val < state.num_triggers) {
 402         state.tselect = val;
 403       }
 404       break;
 405     case CSR_TDATA1:
 406       {
 407         mcontrol_t *mc = &state.mcontrol[state.tselect];
 408         if (mc->dmode && !state.dcsr.cause) {
 409           break;
 410         }
 411         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 412         mc->select = get_field(val, MCONTROL_SELECT);
 413         mc->timing = get_field(val, MCONTROL_TIMING);
 414         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 415         mc->chain = get_field(val, MCONTROL_CHAIN);
 416         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 417         mc->m = get_field(val, MCONTROL_M);
 418         mc->h = get_field(val, MCONTROL_H);
 419         mc->s = get_field(val, MCONTROL_S);
 420         mc->u = get_field(val, MCONTROL_U);
 421         mc->execute = get_field(val, MCONTROL_EXECUTE);
 422         mc->store = get_field(val, MCONTROL_STORE);
 423         mc->load = get_field(val, MCONTROL_LOAD);
 424         // Assume we're here because of csrw.
 425         if (mc->execute)
 426           mc->timing = 0;
 427         trigger_updated();
 428       }
 429       break;
 430     case CSR_TDATA2:
 431       if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
 432         break;
 433       }
 434       if (state.tselect < state.num_triggers) {
 435         state.tdata2[state.tselect] = val;
 436       }
 437       break;
 438     case CSR_DCSR:
 439       state.dcsr.prv = get_field(val, DCSR_PRV);
 440       state.dcsr.step = get_field(val, DCSR_STEP);
 441       // TODO: ndreset and fullreset
 442       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 443       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 444       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 445       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 446       state.dcsr.halt = get_field(val, DCSR_HALT);
 447       break;
 448     case CSR_DPC:
 449       state.dpc = val;
 450       break;
 451     case CSR_DSCRATCH:
 452       state.dscratch = val;
 453       break;
 454   }
 455 }
 456
 457 reg_t processor_t::get_csr(int which)
 458 {
 459   reg_t ctr_en = state.prv == PRV_U ? state.mucounteren :
 460                  state.prv == PRV_S ? state.mscounteren : -1U;
 461   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 462
 463   if (ctr_ok) {
 464     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 465       return 0;
 466     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 467       return 0;
 468   }
 469   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 470     return 0;
 471   if (xlen == 32 && which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 472     return 0;
 473   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 474     return 0;
 475
 476   switch (which)
 477   {
 478     case CSR_FFLAGS:
 479       require_fp;
 480       if (!supports_extension('F'))
 481         break;
 482       return state.fflags;
 483     case CSR_FRM:
 484       require_fp;
 485       if (!supports_extension('F'))
 486         break;
 487       return state.frm;
 488     case CSR_FCSR:
 489       require_fp;
 490       if (!supports_extension('F'))
 491         break;
 492       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 493     case CSR_INSTRET:
 494     case CSR_CYCLE:
 495       if (ctr_ok)
 496         return state.minstret;
 497       break;
 498     case CSR_MINSTRET:
 499     case CSR_MCYCLE:
 500       return state.minstret;
 501     case CSR_MINSTRETH:
 502     case CSR_MCYCLEH:
 503       if (xlen == 32)
 504         return state.minstret >> 32;
 505       break;
 506     case CSR_MUCOUNTEREN: return state.mucounteren;
 507     case CSR_MSCOUNTEREN: return state.mscounteren;
 508     case CSR_SSTATUS: {
 509       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 510                  | SSTATUS_XS | SSTATUS_PUM;
 511       reg_t sstatus = state.mstatus & mask;
 512       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 513           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 514         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 515       return sstatus;
 516     }
 517     case CSR_SIP: return state.mip & state.mideleg;
 518     case CSR_SIE: return state.mie & state.mideleg;
 519     case CSR_SEPC: return state.sepc;
 520     case CSR_SBADADDR: return state.sbadaddr;
 521     case CSR_STVEC: return state.stvec;
 522     case CSR_SCAUSE:
 523       if (max_xlen > xlen)
 524         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 525       return state.scause;
 526     case CSR_SPTBR: return state.sptbr;
 527     case CSR_SSCRATCH: return state.sscratch;
 528     case CSR_MSTATUS: return state.mstatus;
 529     case CSR_MIP: return state.mip;
 530     case CSR_MIE: return state.mie;
 531     case CSR_MEPC: return state.mepc;
 532     case CSR_MSCRATCH: return state.mscratch;
 533     case CSR_MCAUSE: return state.mcause;
 534     case CSR_MBADADDR: return state.mbadaddr;
 535     case CSR_MISA: return isa;
 536     case CSR_MARCHID: return 0;
 537     case CSR_MIMPID: return 0;
 538     case CSR_MVENDORID: return 0;
 539     case CSR_MHARTID: return id;
 540     case CSR_MTVEC: return state.mtvec;
 541     case CSR_MEDELEG: return state.medeleg;
 542     case CSR_MIDELEG: return state.mideleg;
 543     case CSR_TSELECT: return state.tselect;
 544     case CSR_TDATA1:
 545       if (state.tselect < state.num_triggers) {
 546         reg_t v = 0;
 547         mcontrol_t *mc = &state.mcontrol[state.tselect];
 548         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 549         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 550         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 551         v = set_field(v, MCONTROL_SELECT, mc->select);
 552         v = set_field(v, MCONTROL_TIMING, mc->timing);
 553         v = set_field(v, MCONTROL_ACTION, mc->action);
 554         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 555         v = set_field(v, MCONTROL_MATCH, mc->match);
 556         v = set_field(v, MCONTROL_M, mc->m);
 557         v = set_field(v, MCONTROL_H, mc->h);
 558         v = set_field(v, MCONTROL_S, mc->s);
 559         v = set_field(v, MCONTROL_U, mc->u);
 560         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 561         v = set_field(v, MCONTROL_STORE, mc->store);
 562         v = set_field(v, MCONTROL_LOAD, mc->load);
 563         return v;
 564       } else {
 565         return 0;
 566       }
 567       break;
 568     case CSR_TDATA2:
 569       if (state.tselect < state.num_triggers) {
 570         return state.tdata2[state.tselect];
 571       } else {
 572         return 0;
 573       }
 574       break;
 575     case CSR_TDATA3: return 0;
 576     case CSR_DCSR:
 577       {
 578         uint32_t v = 0;
 579         v = set_field(v, DCSR_XDEBUGVER, 1);
 580         v = set_field(v, DCSR_NDRESET, 0);
 581         v = set_field(v, DCSR_FULLRESET, 0);
 582         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 583         v = set_field(v, DCSR_STEP, state.dcsr.step);
 584         v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id));
 585         v = set_field(v, DCSR_STOPCYCLE, 0);
 586         v = set_field(v, DCSR_STOPTIME, 0);
 587         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 588         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 589         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 590         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 591         v = set_field(v, DCSR_HALT, state.dcsr.halt);
 592         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 593         return v;
 594       }
 595     case CSR_DPC:
 596       return state.dpc;
 597     case CSR_DSCRATCH:
 598       return state.dscratch;
 599   }
 600   throw trap_illegal_instruction();
 601 }
 602
 603 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 604 {
 605   throw trap_illegal_instruction();
 606 }
 607
 608 insn_func_t processor_t::decode_insn(insn_t insn)
 609 {
 610   // look up opcode in hash table
 611   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 612   insn_desc_t desc = opcode_cache[idx];
 613
 614   if (unlikely(insn.bits() != desc.match)) {
 615     // fall back to linear search
 616     insn_desc_t* p = &instructions[0];
 617     while ((insn.bits() & p->mask) != p->match)
 618       p++;
 619     desc = *p;
 620
 621     if (p->mask != 0 && p > &instructions[0]) {
 622       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 623         // move to front of opcode list to reduce miss penalty
 624         while (--p >= &instructions[0])
 625           *(p+1) = *p;
 626         instructions[0] = desc;
 627       }
 628     }
 629
 630     opcode_cache[idx] = desc;
 631     opcode_cache[idx].match = insn.bits();
 632   }
 633
 634   return xlen == 64 ? desc.rv64 : desc.rv32;
 635 }
 636
 637 void processor_t::register_insn(insn_desc_t desc)
 638 {
 639   instructions.push_back(desc);
 640 }
 641
 642 void processor_t::build_opcode_map()
 643 {
 644   struct cmp {
 645     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 646       if (lhs.match == rhs.match)
 647         return lhs.mask > rhs.mask;
 648       return lhs.match > rhs.match;
 649     }
 650   };
 651   std::sort(instructions.begin(), instructions.end(), cmp());
 652
 653   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 654     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 655 }
 656
 657 void processor_t::register_extension(extension_t* x)
 658 {
 659   for (auto insn : x->get_instructions())
 660     register_insn(insn);
 661   build_opcode_map();
 662   for (auto disasm_insn : x->get_disasms())
 663     disassembler->add_insn(disasm_insn);
 664   if (ext != NULL)
 665     throw std::logic_error("only one extension may be registered");
 666   ext = x;
 667   x->set_processor(this);
 668 }
 669
 670 void processor_t::register_base_instructions()
 671 {
 672   #define DECLARE_INSN(name, match, mask) \
 673     insn_bits_t name##_match = (match), name##_mask = (mask);
 674   #include "encoding.h"
 675   #undef DECLARE_INSN
 676
 677   #define DEFINE_INSN(name) \
 678     REGISTER_INSN(this, name, name##_match, name##_mask)
 679   #include "insn_list.h"
 680   #undef DEFINE_INSN
 681
 682   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 683   build_opcode_map();
 684 }
 685
 686 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 687 {
 688   switch (addr)
 689   {
 690     case 0:
 691       if (len <= 4) {
 692         memset(bytes, 0, len);
 693         bytes[0] = get_field(state.mip, MIP_MSIP);
 694         return true;
 695       }
 696       break;
 697   }
 698
 699   return false;
 700 }
 701
 702 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 703 {
 704   switch (addr)
 705   {
 706     case 0:
 707       if (len <= 4) {
 708         state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
 709         return true;
 710       }
 711       break;
 712   }
 713
 714   return false;
 715 }
 716
 717 void processor_t::trigger_updated()
 718 {
 719   mmu->flush_tlb();
 720   mmu->check_triggers_fetch = false;
 721   mmu->check_triggers_load = false;
 722   mmu->check_triggers_store = false;
 723
 724   for (unsigned i = 0; i < state.num_triggers; i++) {
 725     if (state.mcontrol[i].execute) {
 726       mmu->check_triggers_fetch = true;
 727     }
 728     if (state.mcontrol[i].load) {
 729       mmu->check_triggers_load = true;
 730     }
 731     if (state.mcontrol[i].store) {
 732       mmu->check_triggers_store = true;
 733     }
 734   }
 735 }