riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
  23         bool halt_on_reset)
  24   : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
  25   halt_on_reset(halt_on_reset), last_pc(1), executions(1)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31   disassembler = new disassembler_t(max_xlen);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdqc";
  65
  66   max_xlen = 64;
  67   isa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, isa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = "imafdc";
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87   isa |= 1L << ('u' - 'a'); // advertise support for user mode
  88
  89   while (*p) {
  90     isa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   if (supports_extension('Q') && !supports_extension('D'))
 110     bad_isa_string(str);
 111
 112   if (supports_extension('Q') && max_xlen < 64)
 113     bad_isa_string(str);
 114
 115   max_isa = isa;
 116 }
 117
 118 void state_t::reset()
 119 {
 120   memset(this, 0, sizeof(*this));
 121   prv = PRV_M;
 122   pc = DEFAULT_RSTVEC;
 123   load_reservation = -1;
 124   tselect = 0;
 125   for (unsigned int i = 0; i < num_triggers; i++)
 126     mcontrol[i].type = 2;
 127 }
 128
 129 void processor_t::set_debug(bool value)
 130 {
 131   debug = value;
 132   if (ext)
 133     ext->set_debug(value);
 134 }
 135
 136 void processor_t::set_histogram(bool value)
 137 {
 138   histogram_enabled = value;
 139 #ifndef RISCV_ENABLE_HISTOGRAM
 140   if (value) {
 141     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 142     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 143   }
 144 #endif
 145 }
 146
 147 void processor_t::reset()
 148 {
 149   state.reset();
 150   state.dcsr.halt = halt_on_reset;
 151   halt_on_reset = false;
 152   set_csr(CSR_MSTATUS, state.mstatus);
 153
 154   if (ext)
 155     ext->reset(); // reset the extension
 156 }
 157
 158 // Count number of contiguous 0 bits starting from the LSB.
 159 static int ctz(reg_t val)
 160 {
 161   int res = 0;
 162   if (val)
 163     while ((val & 1) == 0)
 164       val >>= 1, res++;
 165   return res;
 166 }
 167
 168 void processor_t::take_interrupt(reg_t pending_interrupts)
 169 {
 170   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 171   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 172   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 173
 174   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 175   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 176   if (enabled_interrupts == 0)
 177     enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
 178
 179   if (state.dcsr.cause == 0 && enabled_interrupts)
 180     throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
 181 }
 182
 183 static int xlen_to_uxl(int xlen)
 184 {
 185   if (xlen == 32)
 186     return 1;
 187   if (xlen == 64)
 188     return 2;
 189   abort();
 190 }
 191
 192 reg_t processor_t::legalize_privilege(reg_t prv)
 193 {
 194   assert(prv <= PRV_M);
 195
 196   if (!supports_extension('U'))
 197     return PRV_M;
 198
 199   if (prv == PRV_H || !supports_extension('S'))
 200     return PRV_U;
 201
 202   return prv;
 203 }
 204
 205 void processor_t::set_privilege(reg_t prv)
 206 {
 207   mmu->flush_tlb();
 208   state.prv = legalize_privilege(prv);
 209 }
 210
 211 void processor_t::enter_debug_mode(uint8_t cause)
 212 {
 213   state.dcsr.cause = cause;
 214   state.dcsr.prv = state.prv;
 215   set_privilege(PRV_M);
 216   state.dpc = state.pc;
 217   state.pc = DEBUG_ROM_ENTRY;
 218 }
 219
 220 void processor_t::take_trap(trap_t& t, reg_t epc)
 221 {
 222   if (debug) {
 223     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 224             id, t.name(), epc);
 225     if (t.has_badaddr())
 226       fprintf(stderr, "core %3d:           badaddr 0x%016" PRIx64 "\n", id,
 227           t.get_badaddr());
 228   }
 229
 230   if (state.dcsr.cause) {
 231     if (t.cause() == CAUSE_BREAKPOINT) {
 232       state.pc = DEBUG_ROM_ENTRY;
 233     } else {
 234       state.pc = DEBUG_ROM_TVEC;
 235     }
 236     return;
 237   }
 238
 239   if (t.cause() == CAUSE_BREAKPOINT && (
 240               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 241               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 242               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 243     enter_debug_mode(DCSR_CAUSE_SWBP);
 244     return;
 245   }
 246
 247   // by default, trap to M-mode, unless delegated to S-mode
 248   reg_t bit = t.cause();
 249   reg_t deleg = state.medeleg;
 250   bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
 251   if (interrupt)
 252     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 253   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 254     // handle the trap in S-mode
 255     state.pc = state.stvec;
 256     state.scause = t.cause();
 257     state.sepc = epc;
 258     if (t.has_badaddr())
 259       state.sbadaddr = t.get_badaddr();
 260
 261     reg_t s = state.mstatus;
 262     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
 263     s = set_field(s, MSTATUS_SPP, state.prv);
 264     s = set_field(s, MSTATUS_SIE, 0);
 265     set_csr(CSR_MSTATUS, s);
 266     set_privilege(PRV_S);
 267   } else {
 268     reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0;
 269     state.pc = (state.mtvec & ~(reg_t)1) + vector;
 270     state.mepc = epc;
 271     state.mcause = t.cause();
 272     if (t.has_badaddr())
 273       state.mbadaddr = t.get_badaddr();
 274
 275     reg_t s = state.mstatus;
 276     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
 277     s = set_field(s, MSTATUS_MPP, state.prv);
 278     s = set_field(s, MSTATUS_MIE, 0);
 279     set_csr(CSR_MSTATUS, s);
 280     set_privilege(PRV_M);
 281   }
 282
 283   yield_load_reservation();
 284 }
 285
 286 void processor_t::disasm(insn_t insn)
 287 {
 288   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 289   if (last_pc != state.pc || last_bits != bits) {
 290     if (executions != 1) {
 291       fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions);
 292     }
 293
 294     fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 295             id, state.pc, bits, disassembler->disassemble(insn).c_str());
 296     last_pc = state.pc;
 297     last_bits = bits;
 298     executions = 1;
 299   } else {
 300     executions++;
 301   }
 302 }
 303
 304 int processor_t::paddr_bits()
 305 {
 306   assert(xlen == max_xlen);
 307   return max_xlen == 64 ? 50 : 34;
 308 }
 309
 310 void processor_t::set_csr(int which, reg_t val)
 311 {
 312   val = zext_xlen(val);
 313   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 314   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 315   switch (which)
 316   {
 317     case CSR_FFLAGS:
 318       dirty_fp_state;
 319       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 320       break;
 321     case CSR_FRM:
 322       dirty_fp_state;
 323       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 324       break;
 325     case CSR_FCSR:
 326       dirty_fp_state;
 327       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 328       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 329       break;
 330     case CSR_MSTATUS: {
 331       if ((val ^ state.mstatus) &
 332           (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
 333         mmu->flush_tlb();
 334
 335       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 336                  | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
 337                  | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
 338                  | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL |
 339                  (ext ? MSTATUS_XS : 0);
 340
 341       reg_t requested_mpp = legalize_privilege(get_field(val, MSTATUS_MPP));
 342       state.mstatus = set_field(state.mstatus, MSTATUS_MPP, requested_mpp);
 343       if (supports_extension('S'))
 344         mask |= MSTATUS_SPP;
 345
 346       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 347
 348       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 349       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 350       if (max_xlen == 32)
 351         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 352       else
 353         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 354
 355       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 356       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 357       state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen));
 358       // U-XLEN == S-XLEN == M-XLEN
 359       xlen = max_xlen;
 360       break;
 361     }
 362     case CSR_MIP: {
 363       reg_t mask = MIP_SSIP | MIP_STIP;
 364       state.mip = (state.mip & ~mask) | (val & mask);
 365       break;
 366     }
 367     case CSR_MIE:
 368       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 369       break;
 370     case CSR_MIDELEG:
 371       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 372       break;
 373     case CSR_MEDELEG: {
 374       reg_t mask =
 375         (1 << CAUSE_MISALIGNED_FETCH) |
 376         (1 << CAUSE_BREAKPOINT) |
 377         (1 << CAUSE_USER_ECALL) |
 378         (1 << CAUSE_FETCH_PAGE_FAULT) |
 379         (1 << CAUSE_LOAD_PAGE_FAULT) |
 380         (1 << CAUSE_STORE_PAGE_FAULT);
 381       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 382       break;
 383     }
 384     case CSR_MINSTRET:
 385     case CSR_MCYCLE:
 386       if (xlen == 32)
 387         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 388       else
 389         state.minstret = val;
 390       break;
 391     case CSR_MINSTRETH:
 392     case CSR_MCYCLEH:
 393       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 394       break;
 395     case CSR_SCOUNTEREN:
 396       state.scounteren = val;
 397       break;
 398     case CSR_MCOUNTEREN:
 399       state.mcounteren = val;
 400       break;
 401     case CSR_SSTATUS: {
 402       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 403                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
 404       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 405     }
 406     case CSR_SIP: {
 407       reg_t mask = MIP_SSIP & state.mideleg;
 408       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
 409     }
 410     case CSR_SIE:
 411       return set_csr(CSR_MIE,
 412                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 413     case CSR_SPTBR: {
 414       mmu->flush_tlb();
 415       if (max_xlen == 32)
 416         state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE);
 417       if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF ||
 418                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV39 ||
 419                              get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV48))
 420         state.sptbr = val & (SPTBR64_PPN | SPTBR64_MODE);
 421       break;
 422     }
 423     case CSR_SEPC: state.sepc = val; break;
 424     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 425     case CSR_SSCRATCH: state.sscratch = val; break;
 426     case CSR_SCAUSE: state.scause = val; break;
 427     case CSR_SBADADDR: state.sbadaddr = val; break;
 428     case CSR_MEPC: state.mepc = val; break;
 429     case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
 430     case CSR_MSCRATCH: state.mscratch = val; break;
 431     case CSR_MCAUSE: state.mcause = val; break;
 432     case CSR_MBADADDR: state.mbadaddr = val; break;
 433     case CSR_MISA: {
 434       if (!(val & (1L << ('F' - 'A'))))
 435         val &= ~(1L << ('D' - 'A'));
 436
 437       // allow MAFDC bits in MISA to be modified
 438       reg_t mask = 0;
 439       mask |= 1L << ('M' - 'A');
 440       mask |= 1L << ('A' - 'A');
 441       mask |= 1L << ('F' - 'A');
 442       mask |= 1L << ('D' - 'A');
 443       mask |= 1L << ('C' - 'A');
 444       mask &= max_isa;
 445
 446       isa = (val & mask) | (isa & ~mask);
 447       break;
 448     }
 449     case CSR_TSELECT:
 450       if (val < state.num_triggers) {
 451         state.tselect = val;
 452       }
 453       break;
 454     case CSR_TDATA1:
 455       {
 456         mcontrol_t *mc = &state.mcontrol[state.tselect];
 457         if (mc->dmode && !state.dcsr.cause) {
 458           break;
 459         }
 460         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 461         mc->select = get_field(val, MCONTROL_SELECT);
 462         mc->timing = get_field(val, MCONTROL_TIMING);
 463         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 464         mc->chain = get_field(val, MCONTROL_CHAIN);
 465         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 466         mc->m = get_field(val, MCONTROL_M);
 467         mc->h = get_field(val, MCONTROL_H);
 468         mc->s = get_field(val, MCONTROL_S);
 469         mc->u = get_field(val, MCONTROL_U);
 470         mc->execute = get_field(val, MCONTROL_EXECUTE);
 471         mc->store = get_field(val, MCONTROL_STORE);
 472         mc->load = get_field(val, MCONTROL_LOAD);
 473         // Assume we're here because of csrw.
 474         if (mc->execute)
 475           mc->timing = 0;
 476         trigger_updated();
 477       }
 478       break;
 479     case CSR_TDATA2:
 480       if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
 481         break;
 482       }
 483       if (state.tselect < state.num_triggers) {
 484         state.tdata2[state.tselect] = val;
 485       }
 486       break;
 487     case CSR_DCSR:
 488       state.dcsr.prv = get_field(val, DCSR_PRV);
 489       state.dcsr.step = get_field(val, DCSR_STEP);
 490       // TODO: ndreset and fullreset
 491       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 492       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 493       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 494       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 495       state.dcsr.halt = get_field(val, DCSR_HALT);
 496       break;
 497     case CSR_DPC:
 498       state.dpc = val;
 499       break;
 500     case CSR_DSCRATCH:
 501       state.dscratch = val;
 502       break;
 503   }
 504 }
 505
 506 reg_t processor_t::get_csr(int which)
 507 {
 508   uint32_t ctr_en = -1;
 509   if (state.prv < PRV_M)
 510     ctr_en &= state.mcounteren;
 511   if (state.prv < PRV_S)
 512     ctr_en &= state.scounteren;
 513   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 514
 515   if (ctr_ok) {
 516     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 517       return 0;
 518     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 519       return 0;
 520   }
 521   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 522     return 0;
 523   if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H)
 524     return 0;
 525   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 526     return 0;
 527
 528   switch (which)
 529   {
 530     case CSR_FFLAGS:
 531       require_fp;
 532       if (!supports_extension('F'))
 533         break;
 534       return state.fflags;
 535     case CSR_FRM:
 536       require_fp;
 537       if (!supports_extension('F'))
 538         break;
 539       return state.frm;
 540     case CSR_FCSR:
 541       require_fp;
 542       if (!supports_extension('F'))
 543         break;
 544       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 545     case CSR_INSTRET:
 546     case CSR_CYCLE:
 547       if (ctr_ok)
 548         return state.minstret;
 549       break;
 550     case CSR_MINSTRET:
 551     case CSR_MCYCLE:
 552       return state.minstret;
 553     case CSR_MINSTRETH:
 554     case CSR_MCYCLEH:
 555       if (xlen == 32)
 556         return state.minstret >> 32;
 557       break;
 558     case CSR_SCOUNTEREN: return state.scounteren;
 559     case CSR_MCOUNTEREN: return state.mcounteren;
 560     case CSR_SSTATUS: {
 561       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 562                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_UXL;
 563       reg_t sstatus = state.mstatus & mask;
 564       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 565           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 566         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 567       return sstatus;
 568     }
 569     case CSR_SIP: return state.mip & state.mideleg;
 570     case CSR_SIE: return state.mie & state.mideleg;
 571     case CSR_SEPC: return state.sepc;
 572     case CSR_SBADADDR: return state.sbadaddr;
 573     case CSR_STVEC: return state.stvec;
 574     case CSR_SCAUSE:
 575       if (max_xlen > xlen)
 576         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 577       return state.scause;
 578     case CSR_SPTBR:
 579       if (get_field(state.mstatus, MSTATUS_TVM))
 580         require_privilege(PRV_M);
 581       return state.sptbr;
 582     case CSR_SSCRATCH: return state.sscratch;
 583     case CSR_MSTATUS: return state.mstatus;
 584     case CSR_MIP: return state.mip;
 585     case CSR_MIE: return state.mie;
 586     case CSR_MEPC: return state.mepc;
 587     case CSR_MSCRATCH: return state.mscratch;
 588     case CSR_MCAUSE: return state.mcause;
 589     case CSR_MBADADDR: return state.mbadaddr;
 590     case CSR_MISA: return isa;
 591     case CSR_MARCHID: return 0;
 592     case CSR_MIMPID: return 0;
 593     case CSR_MVENDORID: return 0;
 594     case CSR_MHARTID: return id;
 595     case CSR_MTVEC: return state.mtvec;
 596     case CSR_MEDELEG: return state.medeleg;
 597     case CSR_MIDELEG: return state.mideleg;
 598     case CSR_TSELECT: return state.tselect;
 599     case CSR_TDATA1:
 600       if (state.tselect < state.num_triggers) {
 601         reg_t v = 0;
 602         mcontrol_t *mc = &state.mcontrol[state.tselect];
 603         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 604         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 605         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 606         v = set_field(v, MCONTROL_SELECT, mc->select);
 607         v = set_field(v, MCONTROL_TIMING, mc->timing);
 608         v = set_field(v, MCONTROL_ACTION, mc->action);
 609         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 610         v = set_field(v, MCONTROL_MATCH, mc->match);
 611         v = set_field(v, MCONTROL_M, mc->m);
 612         v = set_field(v, MCONTROL_H, mc->h);
 613         v = set_field(v, MCONTROL_S, mc->s);
 614         v = set_field(v, MCONTROL_U, mc->u);
 615         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 616         v = set_field(v, MCONTROL_STORE, mc->store);
 617         v = set_field(v, MCONTROL_LOAD, mc->load);
 618         return v;
 619       } else {
 620         return 0;
 621       }
 622       break;
 623     case CSR_TDATA2:
 624       if (state.tselect < state.num_triggers) {
 625         return state.tdata2[state.tselect];
 626       } else {
 627         return 0;
 628       }
 629       break;
 630     case CSR_TDATA3: return 0;
 631     case CSR_DCSR:
 632       {
 633         uint32_t v = 0;
 634         v = set_field(v, DCSR_XDEBUGVER, 1);
 635         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 636         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 637         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 638         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 639         v = set_field(v, DCSR_STOPCYCLE, 0);
 640         v = set_field(v, DCSR_STOPTIME, 0);
 641         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 642         v = set_field(v, DCSR_STEP, state.dcsr.step);
 643         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 644         return v;
 645       }
 646     case CSR_DPC:
 647       return state.dpc;
 648     case CSR_DSCRATCH:
 649       return state.dscratch;
 650   }
 651   throw trap_illegal_instruction(0);
 652 }
 653
 654 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 655 {
 656   throw trap_illegal_instruction(0);
 657 }
 658
 659 insn_func_t processor_t::decode_insn(insn_t insn)
 660 {
 661   // look up opcode in hash table
 662   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 663   insn_desc_t desc = opcode_cache[idx];
 664
 665   if (unlikely(insn.bits() != desc.match)) {
 666     // fall back to linear search
 667     insn_desc_t* p = &instructions[0];
 668     while ((insn.bits() & p->mask) != p->match)
 669       p++;
 670     desc = *p;
 671
 672     if (p->mask != 0 && p > &instructions[0]) {
 673       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 674         // move to front of opcode list to reduce miss penalty
 675         while (--p >= &instructions[0])
 676           *(p+1) = *p;
 677         instructions[0] = desc;
 678       }
 679     }
 680
 681     opcode_cache[idx] = desc;
 682     opcode_cache[idx].match = insn.bits();
 683   }
 684
 685   return xlen == 64 ? desc.rv64 : desc.rv32;
 686 }
 687
 688 void processor_t::register_insn(insn_desc_t desc)
 689 {
 690   instructions.push_back(desc);
 691 }
 692
 693 void processor_t::build_opcode_map()
 694 {
 695   struct cmp {
 696     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 697       if (lhs.match == rhs.match)
 698         return lhs.mask > rhs.mask;
 699       return lhs.match > rhs.match;
 700     }
 701   };
 702   std::sort(instructions.begin(), instructions.end(), cmp());
 703
 704   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 705     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 706 }
 707
 708 void processor_t::register_extension(extension_t* x)
 709 {
 710   for (auto insn : x->get_instructions())
 711     register_insn(insn);
 712   build_opcode_map();
 713   for (auto disasm_insn : x->get_disasms())
 714     disassembler->add_insn(disasm_insn);
 715   if (ext != NULL)
 716     throw std::logic_error("only one extension may be registered");
 717   ext = x;
 718   x->set_processor(this);
 719 }
 720
 721 void processor_t::register_base_instructions()
 722 {
 723   #define DECLARE_INSN(name, match, mask) \
 724     insn_bits_t name##_match = (match), name##_mask = (mask);
 725   #include "encoding.h"
 726   #undef DECLARE_INSN
 727
 728   #define DEFINE_INSN(name) \
 729     REGISTER_INSN(this, name, name##_match, name##_mask)
 730   #include "insn_list.h"
 731   #undef DEFINE_INSN
 732
 733   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 734   build_opcode_map();
 735 }
 736
 737 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 738 {
 739   switch (addr)
 740   {
 741     case 0:
 742       if (len <= 4) {
 743         memset(bytes, 0, len);
 744         bytes[0] = get_field(state.mip, MIP_MSIP);
 745         return true;
 746       }
 747       break;
 748   }
 749
 750   return false;
 751 }
 752
 753 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 754 {
 755   switch (addr)
 756   {
 757     case 0:
 758       if (len <= 4) {
 759         state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
 760         return true;
 761       }
 762       break;
 763   }
 764
 765   return false;
 766 }
 767
 768 void processor_t::trigger_updated()
 769 {
 770   mmu->flush_tlb();
 771   mmu->check_triggers_fetch = false;
 772   mmu->check_triggers_load = false;
 773   mmu->check_triggers_store = false;
 774
 775   for (unsigned i = 0; i < state.num_triggers; i++) {
 776     if (state.mcontrol[i].execute) {
 777       mmu->check_triggers_fetch = true;
 778     }
 779     if (state.mcontrol[i].load) {
 780       mmu->check_triggers_load = true;
 781     }
 782     if (state.mcontrol[i].store) {
 783       mmu->check_triggers_store = true;
 784     }
 785   }
 786 }