riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "htif.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
  23   : sim(_sim), mmu(_mmu), ext(NULL), disassembler(new disassembler_t),
  24     id(_id), run(false), debug(false)
  25 {
  26   reset(true);
  27   mmu->set_processor(this);
  28
  29   #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
  30   #include "encoding.h"
  31   #undef DECLARE_INSN
  32   build_opcode_map();
  33 }
  34
  35 processor_t::~processor_t()
  36 {
  37 #ifdef RISCV_ENABLE_HISTOGRAM
  38   if (histogram_enabled)
  39   {
  40     fprintf(stderr, "PC Histogram size:%lu\n", pc_histogram.size());
  41     for(auto iterator = pc_histogram.begin(); iterator != pc_histogram.end(); ++iterator) {
  42       fprintf(stderr, "%0lx %lu\n", (iterator->first << 2), iterator->second);
  43     }
  44   }
  45 #endif
  46
  47   delete disassembler;
  48 }
  49
  50 void state_t::reset()
  51 {
  52   memset(this, 0, sizeof(*this));
  53   mstatus = set_field(mstatus, MSTATUS_PRV, PRV_M);
  54   mstatus = set_field(mstatus, MSTATUS_PRV1, PRV_S);
  55   mstatus = set_field(mstatus, MSTATUS_PRV2, PRV_S);
  56 #ifdef RISCV_ENABLE_64BIT
  57   mstatus = set_field(mstatus, MSTATUS64_UA, UA_RV64);
  58   mstatus = set_field(mstatus, MSTATUS64_SA, UA_RV64);
  59 #endif
  60   pc = 0x100;
  61   load_reservation = -1;
  62 }
  63
  64 void processor_t::set_debug(bool value)
  65 {
  66   debug = value;
  67   if (ext)
  68     ext->set_debug(value);
  69 }
  70
  71 void processor_t::set_histogram(bool value)
  72 {
  73   histogram_enabled = value;
  74 }
  75
  76 void processor_t::reset(bool value)
  77 {
  78   if (run == !value)
  79     return;
  80   run = !value;
  81
  82   state.reset(); // reset the core
  83   set_csr(CSR_MSTATUS, state.mstatus);
  84
  85   if (ext)
  86     ext->reset(); // reset the extension
  87 }
  88
  89 void processor_t::raise_interrupt(reg_t which)
  90 {
  91   throw trap_t(((reg_t)1 << 63) | which);
  92 }
  93
  94 void processor_t::take_interrupt()
  95 {
  96   int priv = get_field(state.mstatus, MSTATUS_PRV);
  97   int ie = get_field(state.mstatus, MSTATUS_IE);
  98
  99   if (priv < PRV_M || (priv == PRV_M && ie)) {
 100     if (get_field(state.mstatus, MSTATUS_MSIP))
 101       raise_interrupt(IRQ_IPI);
 102
 103     if (state.fromhost != 0)
 104       raise_interrupt(IRQ_HOST);
 105   }
 106
 107   if (priv < PRV_S || (priv == PRV_S && ie)) {
 108     if (get_field(state.mstatus, MSTATUS_SSIP))
 109       raise_interrupt(IRQ_IPI);
 110
 111     if (state.stip && get_field(state.mstatus, MSTATUS_STIE))
 112       raise_interrupt(IRQ_TIMER);
 113   }
 114 }
 115
 116 static void commit_log(state_t* state, reg_t pc, insn_t insn)
 117 {
 118 #ifdef RISCV_ENABLE_COMMITLOG
 119   if (get_field(state->mstatus, MSTATUS_IE)) {
 120     uint64_t mask = (insn.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn.length() * 8))) - 1;
 121     if (state->log_reg_write.addr) {
 122       fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ") %c%2" PRIu64 " 0x%016" PRIx64 "\n",
 123               pc,
 124               insn.bits() & mask,
 125               state->log_reg_write.addr & 1 ? 'f' : 'x',
 126               state->log_reg_write.addr >> 1,
 127               state->log_reg_write.data);
 128     } else {
 129       fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ")\n", pc, insn.bits() & mask);
 130     }
 131   }
 132   state->log_reg_write.addr = 0;
 133 #endif
 134 }
 135
 136 inline void processor_t::update_histogram(size_t pc)
 137 {
 138 #ifdef RISCV_ENABLE_HISTOGRAM
 139   size_t idx = pc >> 2;
 140   pc_histogram[idx]++;
 141 #endif
 142 }
 143
 144 static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
 145 {
 146   reg_t npc = fetch.func(p, fetch.insn, pc);
 147   commit_log(p->get_state(), pc, fetch.insn);
 148   p->update_histogram(pc);
 149   return npc;
 150 }
 151
 152 static void update_timer(state_t* state, size_t instret)
 153 {
 154   uint64_t count0 = (uint64_t)(uint32_t)state->scount;
 155   state->scount += instret;
 156   uint64_t before = count0 - state->stimecmp;
 157   if (int64_t(before ^ (before + instret)) < 0)
 158     state->stip = true;
 159 }
 160
 161 static size_t next_timer(state_t* state)
 162 {
 163   return state->stimecmp - (uint32_t)state->scount;
 164 }
 165
 166 void processor_t::step(size_t n)
 167 {
 168   size_t instret = 0;
 169   reg_t pc = state.pc;
 170   mmu_t* _mmu = mmu;
 171
 172   if (unlikely(!run || !n))
 173     return;
 174   n = std::min(n, next_timer(&state) | 1U);
 175
 176   #define maybe_serialize() \
 177    if (unlikely(pc == PC_SERIALIZE)) { \
 178      pc = state.pc; \
 179      state.serialized = true; \
 180      continue; \
 181    }
 182
 183   try
 184   {
 185     take_interrupt();
 186
 187     if (unlikely(debug))
 188     {
 189       while (instret < n)
 190       {
 191         insn_fetch_t fetch = mmu->load_insn(pc);
 192         if (!state.serialized)
 193           disasm(fetch.insn);
 194         pc = execute_insn(this, pc, fetch);
 195         maybe_serialize();
 196         instret++;
 197         state.pc = pc;
 198       }
 199     }
 200     else while (instret < n)
 201     {
 202       size_t idx = _mmu->icache_index(pc);
 203       auto ic_entry = _mmu->access_icache(pc);
 204
 205       #define ICACHE_ACCESS(idx) { \
 206         insn_fetch_t fetch = ic_entry->data; \
 207         ic_entry++; \
 208         pc = execute_insn(this, pc, fetch); \
 209         if (idx == mmu_t::ICACHE_ENTRIES-1) break; \
 210         if (unlikely(ic_entry->tag != pc)) break; \
 211         instret++; \
 212         state.pc = pc; \
 213       }
 214
 215       switch (idx) {
 216         #include "icache.h"
 217       }
 218
 219       maybe_serialize();
 220       instret++;
 221       state.pc = pc;
 222     }
 223   }
 224   catch(trap_t& t)
 225   {
 226     state.pc = take_trap(t, pc);
 227   }
 228
 229   update_timer(&state, instret);
 230 }
 231
 232 void processor_t::push_privilege_stack()
 233 {
 234   reg_t s = state.mstatus;
 235   s = set_field(s, MSTATUS_PRV2, get_field(state.mstatus, MSTATUS_PRV1));
 236   s = set_field(s, MSTATUS_IE2, get_field(state.mstatus, MSTATUS_IE1));
 237   s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV));
 238   s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE));
 239   s = set_field(s, MSTATUS_PRV, PRV_M);
 240   s = set_field(s, MSTATUS_MPRV, PRV_M);
 241   s = set_field(s, MSTATUS_IE, 0);
 242   set_csr(CSR_MSTATUS, s);
 243 }
 244
 245 void processor_t::pop_privilege_stack()
 246 {
 247   reg_t s = state.mstatus;
 248   s = set_field(s, MSTATUS_PRV, get_field(state.mstatus, MSTATUS_PRV1));
 249   s = set_field(s, MSTATUS_IE, get_field(state.mstatus, MSTATUS_IE1));
 250   s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV2));
 251   s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE2));
 252   s = set_field(s, MSTATUS_PRV2, PRV_U);
 253   s = set_field(s, MSTATUS_IE2, 1);
 254   set_csr(CSR_MSTATUS, s);
 255 }
 256
 257 reg_t processor_t::take_trap(trap_t& t, reg_t epc)
 258 {
 259   if (debug)
 260     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 261             id, t.name(), epc);
 262
 263   reg_t tvec = 0x40 * get_field(state.mstatus, MSTATUS_PRV);
 264   push_privilege_stack();
 265   yield_load_reservation();
 266   state.mcause = t.cause();
 267   state.mepc = epc;
 268   t.side_effects(&state); // might set badvaddr etc.
 269   return tvec;
 270 }
 271
 272 void processor_t::deliver_ipi()
 273 {
 274   state.mstatus |= MSTATUS_MSIP;
 275 }
 276
 277 void processor_t::disasm(insn_t insn)
 278 {
 279   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 280   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 281           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 282 }
 283
 284 static bool validate_priv(reg_t priv)
 285 {
 286   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 287 }
 288
 289 static bool validate_arch(reg_t arch)
 290 {
 291 #ifdef RISCV_ENABLE_64BIT
 292   if (arch == UA_RV64) return true;
 293 #endif
 294   return arch == UA_RV32;
 295 }
 296
 297 static bool validate_vm(reg_t vm)
 298 {
 299   // TODO: VM_SV32 support
 300 #ifdef RISCV_ENABLE_64BIT
 301   if (vm == VM_SV43) return true;
 302 #endif
 303   return vm == VM_MBARE;
 304 }
 305
 306 void processor_t::set_csr(int which, reg_t val)
 307 {
 308   switch (which)
 309   {
 310     case CSR_FFLAGS:
 311       dirty_fp_state;
 312       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 313       break;
 314     case CSR_FRM:
 315       dirty_fp_state;
 316       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 317       break;
 318     case CSR_FCSR:
 319       dirty_fp_state;
 320       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 321       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 322       break;
 323     case CSR_SCYCLE:
 324     case CSR_STIME:
 325     case CSR_SINSTRET:
 326       state.scount = val; break;
 327     case CSR_SCYCLEH:
 328     case CSR_STIMEH:
 329     case CSR_SINSTRETH:
 330       state.scount = (val << 32) | (uint32_t)state.scount;
 331       break;
 332     case CSR_MSTATUS:
 333     {
 334       if ((val ^ state.mstatus) & (MSTATUS_VM | MSTATUS_PRV | MSTATUS_MPRV))
 335         mmu->flush_tlb();
 336
 337       reg_t mask = MSTATUS_SSIP | MSTATUS_MSIP | MSTATUS_IE | MSTATUS_IE1
 338                    | MSTATUS_IE2 | MSTATUS_IE3 | MSTATUS_STIE | MSTATUS_FS;
 339       if (ext)
 340         mask |= MSTATUS_XS;
 341       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 342
 343       if (validate_vm(get_field(val, MSTATUS_VM)))
 344         state.mstatus = (state.mstatus & ~MSTATUS_VM) | (val & MSTATUS_VM);
 345       if (validate_priv(get_field(val, MSTATUS_MPRV)))
 346         state.mstatus = (state.mstatus & ~MSTATUS_MPRV) | (val & MSTATUS_MPRV);
 347       if (validate_priv(get_field(val, MSTATUS_PRV)))
 348         state.mstatus = (state.mstatus & ~MSTATUS_PRV) | (val & MSTATUS_PRV);
 349       if (validate_priv(get_field(val, MSTATUS_PRV1)))
 350         state.mstatus = (state.mstatus & ~MSTATUS_PRV1) | (val & MSTATUS_PRV1);
 351       if (validate_priv(get_field(val, MSTATUS_PRV2)))
 352         state.mstatus = (state.mstatus & ~MSTATUS_PRV2) | (val & MSTATUS_PRV2);
 353       if (validate_priv(get_field(val, MSTATUS_PRV3)))
 354         state.mstatus = (state.mstatus & ~MSTATUS_PRV3) | (val & MSTATUS_PRV3);
 355       xlen = 32;
 356
 357       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 358       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 359 #ifndef RISCV_ENABLE_64BIT
 360       state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 361 #else
 362       state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 363
 364       if (validate_arch(get_field(val, MSTATUS64_UA)))
 365         state.mstatus = (state.mstatus & ~MSTATUS64_UA) | (val & MSTATUS64_UA);
 366       if (validate_arch(get_field(val, MSTATUS64_SA)))
 367         state.mstatus = (state.mstatus & ~MSTATUS64_SA) | (val & MSTATUS64_SA);
 368       switch (get_field(state.mstatus, MSTATUS_PRV)) {
 369         case PRV_U: if (get_field(state.mstatus, MSTATUS64_UA)) xlen = 64; break;
 370         case PRV_S: if (get_field(state.mstatus, MSTATUS64_SA)) xlen = 64; break;
 371         case PRV_M: xlen = 64; break;
 372         default: abort();
 373       }
 374 #endif
 375       break;
 376     }
 377     case CSR_SSTATUS:
 378     {
 379       reg_t ms = state.mstatus;
 380       ms = set_field(ms, MSTATUS_SSIP, get_field(val, SSTATUS_SIP));
 381       ms = set_field(ms, MSTATUS_IE, get_field(val, SSTATUS_IE));
 382       ms = set_field(ms, MSTATUS_IE1, get_field(val, SSTATUS_PIE));
 383       ms = set_field(ms, MSTATUS_PRV1, get_field(val, SSTATUS_PS));
 384       ms = set_field(ms, MSTATUS64_UA, get_field(val, SSTATUS_UA));
 385       ms = set_field(ms, MSTATUS_STIE, get_field(val, SSTATUS_TIE));
 386       ms = set_field(ms, MSTATUS_FS, get_field(val, SSTATUS_FS));
 387       ms = set_field(ms, MSTATUS_XS, get_field(val, SSTATUS_XS));
 388       return set_csr(CSR_MSTATUS, ms);
 389     }
 390     case CSR_SEPC: state.sepc = val; break;
 391     case CSR_STVEC: state.stvec = val & ~3; break;
 392     case CSR_STIMECMP:
 393       state.stip = false;
 394       state.stimecmp = val;
 395       break;
 396     case CSR_SPTBR: state.sptbr = val & ~(PGSIZE-1); break;
 397     case CSR_SSCRATCH: state.sscratch = val; break;
 398     case CSR_MEPC: state.mepc = val; break;
 399     case CSR_MSCRATCH: state.mscratch = val; break;
 400     case CSR_MCAUSE: state.mcause = val; break;
 401     case CSR_MBADADDR: state.mbadaddr = val; break;
 402     case CSR_SEND_IPI: sim->send_ipi(val); break;
 403     case CSR_TOHOST:
 404       if (state.tohost == 0)
 405         state.tohost = val;
 406       break;
 407     case CSR_FROMHOST: state.fromhost = val; break;
 408   }
 409 }
 410
 411 reg_t processor_t::get_csr(int which)
 412 {
 413   switch (which)
 414   {
 415     case CSR_FFLAGS:
 416       require_fp;
 417       return state.fflags;
 418     case CSR_FRM:
 419       require_fp;
 420       return state.frm;
 421     case CSR_FCSR:
 422       require_fp;
 423       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 424     case CSR_CYCLE:
 425     case CSR_TIME:
 426     case CSR_INSTRET:
 427     case CSR_SCYCLE:
 428     case CSR_STIME:
 429     case CSR_SINSTRET:
 430       return state.scount;
 431     case CSR_CYCLEH:
 432     case CSR_TIMEH:
 433     case CSR_INSTRETH:
 434     case CSR_SCYCLEH:
 435     case CSR_STIMEH:
 436     case CSR_SINSTRETH:
 437       if (xlen == 64)
 438         break;
 439       return state.scount >> 32;
 440     case CSR_SSTATUS:
 441     {
 442       reg_t ss = 0;
 443       ss = set_field(ss, SSTATUS_SIP, get_field(state.mstatus, MSTATUS_SSIP));
 444       ss = set_field(ss, SSTATUS_IE, get_field(state.mstatus, MSTATUS_IE));
 445       ss = set_field(ss, SSTATUS_PIE, get_field(state.mstatus, MSTATUS_IE1));
 446       ss = set_field(ss, SSTATUS_PS, get_field(state.mstatus, MSTATUS_PRV1));
 447       ss = set_field(ss, SSTATUS_UA, get_field(state.mstatus, MSTATUS64_UA));
 448       ss = set_field(ss, SSTATUS_TIE, get_field(state.mstatus, MSTATUS_STIE));
 449       ss = set_field(ss, SSTATUS_TIP, state.stip);
 450       ss = set_field(ss, SSTATUS_FS, get_field(state.mstatus, MSTATUS_FS));
 451       ss = set_field(ss, SSTATUS_XS, get_field(state.mstatus, MSTATUS_XS));
 452       if (get_field(state.mstatus, MSTATUS64_SD))
 453         ss = set_field(ss, (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD), 1);
 454       return ss;
 455     }
 456     case CSR_SEPC: return state.sepc;
 457     case CSR_SBADADDR: return state.sbadaddr;
 458     case CSR_STVEC: return state.stvec;
 459     case CSR_STIMECMP: return state.stimecmp;
 460     case CSR_SCAUSE:
 461       if (xlen == 32 && (state.scause >> 63) != 0)
 462         return state.scause | ((reg_t)1 << 31);
 463       return state.scause;
 464     case CSR_SPTBR: return state.sptbr;
 465     case CSR_SASID: return 0;
 466     case CSR_SSCRATCH: return state.sscratch;
 467     case CSR_MSTATUS: return state.mstatus;
 468     case CSR_MEPC: return state.mepc;
 469     case CSR_MSCRATCH: return state.mscratch;
 470     case CSR_MCAUSE: return state.mcause;
 471     case CSR_MBADADDR: return state.mbadaddr;
 472     case CSR_TOHOST:
 473       sim->get_htif()->tick(); // not necessary, but faster
 474       return state.tohost;
 475     case CSR_FROMHOST:
 476       sim->get_htif()->tick(); // not necessary, but faster
 477       return state.fromhost;
 478     case CSR_SEND_IPI: return 0;
 479     case CSR_HARTID: return id;
 480     case CSR_UARCH0:
 481     case CSR_UARCH1:
 482     case CSR_UARCH2:
 483     case CSR_UARCH3:
 484     case CSR_UARCH4:
 485     case CSR_UARCH5:
 486     case CSR_UARCH6:
 487     case CSR_UARCH7:
 488     case CSR_UARCH8:
 489     case CSR_UARCH9:
 490     case CSR_UARCH10:
 491     case CSR_UARCH11:
 492     case CSR_UARCH12:
 493     case CSR_UARCH13:
 494     case CSR_UARCH14:
 495     case CSR_UARCH15:
 496       return 0;
 497   }
 498   throw trap_illegal_instruction();
 499 }
 500
 501 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 502 {
 503   throw trap_illegal_instruction();
 504 }
 505
 506 insn_func_t processor_t::decode_insn(insn_t insn)
 507 {
 508   size_t mask = opcode_map.size()-1;
 509   insn_desc_t* desc = opcode_map[insn.bits() & mask];
 510
 511   while ((insn.bits() & desc->mask) != desc->match)
 512     desc++;
 513
 514   return xlen == 64 ? desc->rv64 : desc->rv32;
 515 }
 516
 517 void processor_t::register_insn(insn_desc_t desc)
 518 {
 519   assert(desc.mask & 1);
 520   instructions.push_back(desc);
 521 }
 522
 523 void processor_t::build_opcode_map()
 524 {
 525   size_t buckets = -1;
 526   for (auto& inst : instructions)
 527     while ((inst.mask & buckets) != buckets)
 528       buckets /= 2;
 529   buckets++;
 530
 531   struct cmp {
 532     decltype(insn_desc_t::match) mask;
 533     cmp(decltype(mask) mask) : mask(mask) {}
 534     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 535       if ((lhs.match & mask) != (rhs.match & mask))
 536         return (lhs.match & mask) < (rhs.match & mask);
 537       return lhs.match < rhs.match;
 538     }
 539   };
 540   std::sort(instructions.begin(), instructions.end(), cmp(buckets-1));
 541
 542   opcode_map.resize(buckets);
 543   opcode_store.resize(instructions.size() + 1);
 544
 545   size_t j = 0;
 546   for (size_t b = 0, i = 0; b < buckets; b++)
 547   {
 548     opcode_map[b] = &opcode_store[j];
 549     while (i < instructions.size() && b == (instructions[i].match & (buckets-1)))
 550       opcode_store[j++] = instructions[i++];
 551   }
 552
 553   assert(j == opcode_store.size()-1);
 554   opcode_store[j].match = opcode_store[j].mask = 0;
 555   opcode_store[j].rv32 = &illegal_instruction;
 556   opcode_store[j].rv64 = &illegal_instruction;
 557 }
 558
 559 void processor_t::register_extension(extension_t* x)
 560 {
 561   for (auto insn : x->get_instructions())
 562     register_insn(insn);
 563   build_opcode_map();
 564   for (auto disasm_insn : x->get_disasms())
 565     disassembler->add_insn(disasm_insn);
 566   if (ext != NULL)
 567     throw std::logic_error("only one extension may be registered");
 568   ext = x;
 569   x->set_processor(this);
 570 }