riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "htif.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
  23   : sim(sim), ext(NULL), disassembler(new disassembler_t),
  24     id(id), run(false), debug(false)
  25 {
  26   parse_isa_string(isa);
  27
  28   mmu = new mmu_t(sim->mem, sim->memsz);
  29   mmu->set_processor(this);
  30
  31   reset(true);
  32
  33   #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
  34   #include "encoding.h"
  35   #undef DECLARE_INSN
  36   build_opcode_map();
  37 }
  38
  39 processor_t::~processor_t()
  40 {
  41 #ifdef RISCV_ENABLE_HISTOGRAM
  42   if (histogram_enabled)
  43   {
  44     fprintf(stderr, "PC Histogram size:%lu\n", pc_histogram.size());
  45     for(auto iterator = pc_histogram.begin(); iterator != pc_histogram.end(); ++iterator) {
  46       fprintf(stderr, "%0lx %lu\n", (iterator->first << 2), iterator->second);
  47     }
  48   }
  49 #endif
  50
  51   delete mmu;
  52   delete disassembler;
  53 }
  54
  55 static void bad_isa_string(const char* isa)
  56 {
  57   fprintf(stderr, "error: bad --isa option %s\n", isa);
  58   abort();
  59 }
  60
  61 void processor_t::parse_isa_string(const char* isa)
  62 {
  63   const char* p = isa;
  64   const char* all_subsets = "IMAFDC";
  65
  66   max_xlen = 64;
  67   cpuid = reg_t(2) << 62;
  68
  69   if (strncmp(p, "RV32", 4) == 0)
  70     max_xlen = 32, cpuid = 0, p += 4;
  71   else if (strncmp(p, "RV64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "RV", 2) == 0)
  74     p += 2;
  75
  76   cpuid |= 1L << ('S' - 'A'); // advertise support for supervisor mode
  77
  78   if (!*p)
  79     p = all_subsets;
  80   else if (*p != 'I')
  81     bad_isa_string(isa);
  82
  83   while (*p) {
  84     cpuid |= 1L << (*p - 'A');
  85
  86     if (auto next = strchr(all_subsets, *p)) {
  87       all_subsets = next + 1;
  88       p++;
  89     } else if (*p == 'X') {
  90       const char* ext = p+1, *end = ext;
  91       while (islower(*end))
  92         end++;
  93       register_extension(find_extension(std::string(ext, end - ext).c_str())());
  94       p = end;
  95     } else {
  96       bad_isa_string(isa);
  97     }
  98   }
  99
 100   if (supports_extension('D') && !supports_extension('F'))
 101     bad_isa_string(isa);
 102 }
 103
 104 void state_t::reset()
 105 {
 106   memset(this, 0, sizeof(*this));
 107   mstatus = set_field(mstatus, MSTATUS_PRV, PRV_M);
 108   mstatus = set_field(mstatus, MSTATUS_PRV1, PRV_S);
 109   mstatus = set_field(mstatus, MSTATUS_PRV2, PRV_S);
 110   pc = DEFAULT_MTVEC + 0x100;
 111   load_reservation = -1;
 112 }
 113
 114 void processor_t::set_debug(bool value)
 115 {
 116   debug = value;
 117   if (ext)
 118     ext->set_debug(value);
 119 }
 120
 121 void processor_t::set_histogram(bool value)
 122 {
 123   histogram_enabled = value;
 124 }
 125
 126 void processor_t::reset(bool value)
 127 {
 128   if (run == !value)
 129     return;
 130   run = !value;
 131
 132   state.reset();
 133   set_csr(CSR_MSTATUS, state.mstatus);
 134
 135   if (ext)
 136     ext->reset(); // reset the extension
 137 }
 138
 139 void processor_t::raise_interrupt(reg_t which)
 140 {
 141   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 142 }
 143
 144 void processor_t::take_interrupt()
 145 {
 146   int priv = get_field(state.mstatus, MSTATUS_PRV);
 147   int ie = get_field(state.mstatus, MSTATUS_IE);
 148   reg_t interrupts = state.mie & state.mip;
 149
 150   if (priv < PRV_M || (priv == PRV_M && ie)) {
 151     if (interrupts & MIP_MSIP)
 152       raise_interrupt(IRQ_SOFT);
 153
 154     if (interrupts & MIP_MTIP)
 155       raise_interrupt(IRQ_TIMER);
 156
 157     if (state.fromhost != 0)
 158       raise_interrupt(IRQ_HOST);
 159   }
 160
 161   if (priv < PRV_S || (priv == PRV_S && ie)) {
 162     if (interrupts & MIP_SSIP)
 163       raise_interrupt(IRQ_SOFT);
 164
 165     if (interrupts & MIP_STIP)
 166       raise_interrupt(IRQ_TIMER);
 167   }
 168 }
 169
 170 static void commit_log(state_t* state, reg_t pc, insn_t insn)
 171 {
 172 #ifdef RISCV_ENABLE_COMMITLOG
 173   if (get_field(state->mstatus, MSTATUS_IE)) {
 174     uint64_t mask = (insn.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn.length() * 8))) - 1;
 175     if (state->log_reg_write.addr) {
 176       fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ") %c%2" PRIu64 " 0x%016" PRIx64 "\n",
 177               pc,
 178               insn.bits() & mask,
 179               state->log_reg_write.addr & 1 ? 'f' : 'x',
 180               state->log_reg_write.addr >> 1,
 181               state->log_reg_write.data);
 182     } else {
 183       fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ")\n", pc, insn.bits() & mask);
 184     }
 185   }
 186   state->log_reg_write.addr = 0;
 187 #endif
 188 }
 189
 190 inline void processor_t::update_histogram(size_t pc)
 191 {
 192 #ifdef RISCV_ENABLE_HISTOGRAM
 193   size_t idx = pc >> 2;
 194   pc_histogram[idx]++;
 195 #endif
 196 }
 197
 198 static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
 199 {
 200   reg_t npc = fetch.func(p, fetch.insn, pc);
 201   if (npc != PC_SERIALIZE) {
 202     commit_log(p->get_state(), pc, fetch.insn);
 203     p->update_histogram(pc);
 204   }
 205   return npc;
 206 }
 207
 208 void processor_t::check_timer()
 209 {
 210   if (sim->rtc >= state.mtimecmp)
 211     state.mip |= MIP_MTIP;
 212 }
 213
 214 void processor_t::step(size_t n)
 215 {
 216   size_t instret = 0;
 217   reg_t pc = state.pc;
 218   mmu_t* _mmu = mmu;
 219
 220   if (unlikely(!run || !n))
 221     return;
 222
 223   #define maybe_serialize() \
 224    if (unlikely(pc == PC_SERIALIZE)) { \
 225      pc = state.pc; \
 226      state.serialized = true; \
 227      break; \
 228    }
 229
 230   try
 231   {
 232     check_timer();
 233     take_interrupt();
 234
 235     if (unlikely(debug))
 236     {
 237       while (instret < n)
 238       {
 239         insn_fetch_t fetch = mmu->load_insn(pc);
 240         if (!state.serialized)
 241           disasm(fetch.insn);
 242         pc = execute_insn(this, pc, fetch);
 243         maybe_serialize();
 244         instret++;
 245         state.pc = pc;
 246       }
 247     }
 248     else while (instret < n)
 249     {
 250       size_t idx = _mmu->icache_index(pc);
 251       auto ic_entry = _mmu->access_icache(pc);
 252
 253       #define ICACHE_ACCESS(idx) { \
 254         insn_fetch_t fetch = ic_entry->data; \
 255         ic_entry++; \
 256         pc = execute_insn(this, pc, fetch); \
 257         if (idx == mmu_t::ICACHE_ENTRIES-1) break; \
 258         if (unlikely(ic_entry->tag != pc)) break; \
 259         if (unlikely(instret+1 == n)) break; \
 260         instret++; \
 261         state.pc = pc; \
 262       }
 263
 264       switch (idx) {
 265         #include "icache.h"
 266       }
 267
 268       maybe_serialize();
 269       instret++;
 270       state.pc = pc;
 271     }
 272   }
 273   catch(trap_t& t)
 274   {
 275     take_trap(t, pc);
 276   }
 277
 278   state.minstret += instret;
 279
 280   // tail-recurse if we didn't execute as many instructions as we'd hoped
 281   if (instret < n)
 282     step(n - instret);
 283 }
 284
 285 void processor_t::push_privilege_stack()
 286 {
 287   reg_t s = state.mstatus;
 288   s = set_field(s, MSTATUS_PRV2, get_field(state.mstatus, MSTATUS_PRV1));
 289   s = set_field(s, MSTATUS_IE2, get_field(state.mstatus, MSTATUS_IE1));
 290   s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV));
 291   s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE));
 292   s = set_field(s, MSTATUS_PRV, PRV_M);
 293   s = set_field(s, MSTATUS_MPRV, 0);
 294   s = set_field(s, MSTATUS_IE, 0);
 295   set_csr(CSR_MSTATUS, s);
 296 }
 297
 298 void processor_t::pop_privilege_stack()
 299 {
 300   reg_t s = state.mstatus;
 301   s = set_field(s, MSTATUS_PRV, get_field(state.mstatus, MSTATUS_PRV1));
 302   s = set_field(s, MSTATUS_IE, get_field(state.mstatus, MSTATUS_IE1));
 303   s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV2));
 304   s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE2));
 305   s = set_field(s, MSTATUS_PRV2, PRV_U);
 306   s = set_field(s, MSTATUS_IE2, 1);
 307   set_csr(CSR_MSTATUS, s);
 308 }
 309
 310 void processor_t::take_trap(trap_t& t, reg_t epc)
 311 {
 312   if (debug)
 313     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 314             id, t.name(), epc);
 315
 316   state.pc = DEFAULT_MTVEC + 0x40 * get_field(state.mstatus, MSTATUS_PRV);
 317   push_privilege_stack();
 318   yield_load_reservation();
 319   state.mcause = t.cause();
 320   state.mepc = epc;
 321   t.side_effects(&state); // might set badvaddr etc.
 322 }
 323
 324 void processor_t::deliver_ipi()
 325 {
 326   state.mip |= MIP_MSIP;
 327 }
 328
 329 void processor_t::disasm(insn_t insn)
 330 {
 331   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 332   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 333           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 334 }
 335
 336 static bool validate_priv(reg_t priv)
 337 {
 338   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 339 }
 340
 341 static bool validate_vm(int max_xlen, reg_t vm)
 342 {
 343   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 344     return true;
 345   if (max_xlen == 32 && vm == VM_SV32)
 346     return true;
 347   return vm == VM_MBARE;
 348 }
 349
 350 void processor_t::set_csr(int which, reg_t val)
 351 {
 352   switch (which)
 353   {
 354     case CSR_FFLAGS:
 355       dirty_fp_state;
 356       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 357       break;
 358     case CSR_FRM:
 359       dirty_fp_state;
 360       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 361       break;
 362     case CSR_FCSR:
 363       dirty_fp_state;
 364       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 365       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 366       break;
 367     case CSR_MTIME:
 368     case CSR_STIMEW:
 369       // this implementation ignores writes to MTIME
 370       break;
 371     case CSR_MTIMEH:
 372     case CSR_STIMEHW:
 373       // this implementation ignores writes to MTIME
 374       break;
 375     case CSR_TIMEW:
 376       val -= sim->rtc;
 377       if (xlen == 32)
 378         state.sutime_delta = (uint32_t)val | (state.sutime_delta >> 32 << 32);
 379       else
 380         state.sutime_delta = val;
 381       break;
 382     case CSR_TIMEHW:
 383       val = ((val << 32) - sim->rtc) >> 32;
 384       state.sutime_delta = (val << 32) | (uint32_t)state.sutime_delta;
 385       break;
 386     case CSR_CYCLEW:
 387     case CSR_INSTRETW:
 388       val -= state.minstret;
 389       if (xlen == 32)
 390         state.suinstret_delta = (uint32_t)val | (state.suinstret_delta >> 32 << 32);
 391       else
 392         state.suinstret_delta = val;
 393       break;
 394     case CSR_CYCLEHW:
 395     case CSR_INSTRETHW:
 396       val = ((val << 32) - state.minstret) >> 32;
 397       state.suinstret_delta = (val << 32) | (uint32_t)state.suinstret_delta;
 398       break;
 399     case CSR_MSTATUS: {
 400       if ((val ^ state.mstatus) & (MSTATUS_VM | MSTATUS_PRV | MSTATUS_PRV1 | MSTATUS_MPRV))
 401         mmu->flush_tlb();
 402
 403       reg_t mask = MSTATUS_IE | MSTATUS_IE1 | MSTATUS_IE2 | MSTATUS_MPRV
 404                    | MSTATUS_FS | (ext ? MSTATUS_XS : 0);
 405
 406       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 407         mask |= MSTATUS_VM;
 408       if (validate_priv(get_field(val, MSTATUS_PRV)))
 409         mask |= MSTATUS_PRV;
 410       if (validate_priv(get_field(val, MSTATUS_PRV1)))
 411         mask |= MSTATUS_PRV1;
 412       if (validate_priv(get_field(val, MSTATUS_PRV2)))
 413         mask |= MSTATUS_PRV2;
 414
 415       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 416
 417       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 418       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 419       if (max_xlen == 32)
 420         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 421       else
 422         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 423
 424       // spike supports the notion of xlen < max_xlen, but current priv spec
 425       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 426       xlen = max_xlen;
 427       break;
 428     }
 429     case CSR_MIP: {
 430       reg_t mask = MIP_SSIP | MIP_MSIP | MIP_STIP;
 431       state.mip = (state.mip & ~mask) | (val & mask);
 432       break;
 433     }
 434     case CSR_MIE: {
 435       reg_t mask = MIP_SSIP | MIP_MSIP | MIP_STIP | MIP_MTIP;
 436       state.mie = (state.mie & ~mask) | (val & mask);
 437       break;
 438     }
 439     case CSR_SSTATUS: {
 440       reg_t ms = state.mstatus;
 441       ms = set_field(ms, MSTATUS_IE, get_field(val, SSTATUS_IE));
 442       ms = set_field(ms, MSTATUS_IE1, get_field(val, SSTATUS_PIE));
 443       ms = set_field(ms, MSTATUS_PRV1, get_field(val, SSTATUS_PS));
 444       ms = set_field(ms, MSTATUS_FS, get_field(val, SSTATUS_FS));
 445       ms = set_field(ms, MSTATUS_XS, get_field(val, SSTATUS_XS));
 446       ms = set_field(ms, MSTATUS_MPRV, get_field(val, SSTATUS_MPRV));
 447       return set_csr(CSR_MSTATUS, ms);
 448     }
 449     case CSR_SIP: {
 450       reg_t mask = MIP_SSIP;
 451       state.mip = (state.mip & ~mask) | (val & mask);
 452       break;
 453     }
 454     case CSR_SIE: {
 455       reg_t mask = MIP_SSIP | MIP_STIP;
 456       state.mie = (state.mie & ~mask) | (val & mask);
 457       break;
 458     }
 459     case CSR_SEPC: state.sepc = val; break;
 460     case CSR_STVEC: state.stvec = val & ~3; break;
 461     case CSR_SPTBR: state.sptbr = zext_xlen(val & -PGSIZE); break;
 462     case CSR_SSCRATCH: state.sscratch = val; break;
 463     case CSR_MEPC: state.mepc = val; break;
 464     case CSR_MSCRATCH: state.mscratch = val; break;
 465     case CSR_MCAUSE: state.mcause = val; break;
 466     case CSR_MBADADDR: state.mbadaddr = val; break;
 467     case CSR_MTIMECMP:
 468       state.mip &= ~MIP_MTIP;
 469       state.mtimecmp = val;
 470       break;
 471     case CSR_SEND_IPI: sim->send_ipi(val); break;
 472     case CSR_MTOHOST:
 473       if (state.tohost == 0)
 474         state.tohost = val;
 475       break;
 476     case CSR_MFROMHOST: state.fromhost = val; break;
 477   }
 478 }
 479
 480 reg_t processor_t::get_csr(int which)
 481 {
 482   switch (which)
 483   {
 484     case CSR_FFLAGS:
 485       require_fp;
 486       if (!supports_extension('F'))
 487         break;
 488       return state.fflags;
 489     case CSR_FRM:
 490       require_fp;
 491       if (!supports_extension('F'))
 492         break;
 493       return state.frm;
 494     case CSR_FCSR:
 495       require_fp;
 496       if (!supports_extension('F'))
 497         break;
 498       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 499     case CSR_MTIME:
 500     case CSR_STIME:
 501     case CSR_STIMEW:
 502       return sim->rtc;
 503     case CSR_MTIMEH:
 504     case CSR_STIMEH:
 505     case CSR_STIMEHW:
 506       return sim->rtc >> 32;
 507     case CSR_TIME:
 508     case CSR_TIMEW:
 509       return sim->rtc + state.sutime_delta;
 510     case CSR_CYCLE:
 511     case CSR_CYCLEW:
 512     case CSR_INSTRET:
 513     case CSR_INSTRETW:
 514       return state.minstret + state.suinstret_delta;
 515     case CSR_TIMEH:
 516     case CSR_TIMEHW:
 517       if (xlen == 64)
 518         break;
 519       return (sim->rtc + state.sutime_delta) >> 32;
 520     case CSR_CYCLEH:
 521     case CSR_INSTRETH:
 522     case CSR_CYCLEHW:
 523     case CSR_INSTRETHW:
 524       if (xlen == 64)
 525         break;
 526       return (state.minstret + state.suinstret_delta) >> 32;
 527     case CSR_SSTATUS: {
 528       reg_t ss = 0;
 529       ss = set_field(ss, SSTATUS_IE, get_field(state.mstatus, MSTATUS_IE));
 530       ss = set_field(ss, SSTATUS_PIE, get_field(state.mstatus, MSTATUS_IE1));
 531       ss = set_field(ss, SSTATUS_PS, get_field(state.mstatus, MSTATUS_PRV1));
 532       ss = set_field(ss, SSTATUS_FS, get_field(state.mstatus, MSTATUS_FS));
 533       ss = set_field(ss, SSTATUS_XS, get_field(state.mstatus, MSTATUS_XS));
 534       ss = set_field(ss, SSTATUS_MPRV, get_field(state.mstatus, MSTATUS_MPRV));
 535       if (get_field(state.mstatus, MSTATUS64_SD))
 536         ss = set_field(ss, (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD), 1);
 537       return ss;
 538     }
 539     case CSR_SIP: return state.mip & (MIP_SSIP | MIP_STIP);
 540     case CSR_SIE: return state.mie & (MIP_SSIP | MIP_STIP);
 541     case CSR_SEPC: return state.sepc;
 542     case CSR_SBADADDR: return state.sbadaddr;
 543     case CSR_STVEC: return state.stvec;
 544     case CSR_SCAUSE:
 545       if (max_xlen > xlen)
 546         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 547       return state.scause;
 548     case CSR_SPTBR: return state.sptbr;
 549     case CSR_SASID: return 0;
 550     case CSR_SSCRATCH: return state.sscratch;
 551     case CSR_MSTATUS: return state.mstatus;
 552     case CSR_MIP: return state.mip;
 553     case CSR_MIE: return state.mie;
 554     case CSR_MEPC: return state.mepc;
 555     case CSR_MSCRATCH: return state.mscratch;
 556     case CSR_MCAUSE: return state.mcause;
 557     case CSR_MBADADDR: return state.mbadaddr;
 558     case CSR_MTIMECMP: return state.mtimecmp;
 559     case CSR_MCPUID: return cpuid;
 560     case CSR_MIMPID: return IMPL_ROCKET;
 561     case CSR_MHARTID: return id;
 562     case CSR_MTVEC: return DEFAULT_MTVEC;
 563     case CSR_MTDELEG: return 0;
 564     case CSR_MTOHOST:
 565       sim->get_htif()->tick(); // not necessary, but faster
 566       return state.tohost;
 567     case CSR_MFROMHOST:
 568       sim->get_htif()->tick(); // not necessary, but faster
 569       return state.fromhost;
 570     case CSR_SEND_IPI: return 0;
 571     case CSR_UARCH0:
 572     case CSR_UARCH1:
 573     case CSR_UARCH2:
 574     case CSR_UARCH3:
 575     case CSR_UARCH4:
 576     case CSR_UARCH5:
 577     case CSR_UARCH6:
 578     case CSR_UARCH7:
 579     case CSR_UARCH8:
 580     case CSR_UARCH9:
 581     case CSR_UARCH10:
 582     case CSR_UARCH11:
 583     case CSR_UARCH12:
 584     case CSR_UARCH13:
 585     case CSR_UARCH14:
 586     case CSR_UARCH15:
 587       return 0;
 588   }
 589   throw trap_illegal_instruction();
 590 }
 591
 592 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 593 {
 594   throw trap_illegal_instruction();
 595 }
 596
 597 insn_func_t processor_t::decode_insn(insn_t insn)
 598 {
 599   size_t mask = opcode_map.size()-1;
 600   insn_desc_t* desc = opcode_map[insn.bits() & mask];
 601
 602   while ((insn.bits() & desc->mask) != desc->match)
 603     desc++;
 604
 605   return xlen == 64 ? desc->rv64 : desc->rv32;
 606 }
 607
 608 void processor_t::register_insn(insn_desc_t desc)
 609 {
 610   assert(desc.mask & 1);
 611   instructions.push_back(desc);
 612 }
 613
 614 void processor_t::build_opcode_map()
 615 {
 616   size_t buckets = -1;
 617   for (auto& inst : instructions)
 618     while ((inst.mask & buckets) != buckets)
 619       buckets /= 2;
 620   buckets++;
 621
 622   struct cmp {
 623     decltype(insn_desc_t::match) mask;
 624     cmp(decltype(mask) mask) : mask(mask) {}
 625     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 626       if ((lhs.match & mask) != (rhs.match & mask))
 627         return (lhs.match & mask) < (rhs.match & mask);
 628       return lhs.match < rhs.match;
 629     }
 630   };
 631   std::sort(instructions.begin(), instructions.end(), cmp(buckets-1));
 632
 633   opcode_map.resize(buckets);
 634   opcode_store.resize(instructions.size() + 1);
 635
 636   size_t j = 0;
 637   for (size_t b = 0, i = 0; b < buckets; b++)
 638   {
 639     opcode_map[b] = &opcode_store[j];
 640     while (i < instructions.size() && b == (instructions[i].match & (buckets-1)))
 641       opcode_store[j++] = instructions[i++];
 642   }
 643
 644   assert(j == opcode_store.size()-1);
 645   opcode_store[j].match = opcode_store[j].mask = 0;
 646   opcode_store[j].rv32 = &illegal_instruction;
 647   opcode_store[j].rv64 = &illegal_instruction;
 648 }
 649
 650 void processor_t::register_extension(extension_t* x)
 651 {
 652   for (auto insn : x->get_instructions())
 653     register_insn(insn);
 654   build_opcode_map();
 655   for (auto disasm_insn : x->get_disasms())
 656     disassembler->add_insn(disasm_insn);
 657   if (ext != NULL)
 658     throw std::logic_error("only one extension may be registered");
 659   ext = x;
 660   x->set_processor(this);
 661 }