riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, simif_t* sim, uint32_t id,
  23         bool halt_on_reset)
  24   : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
  25   halt_on_reset(halt_on_reset), last_pc(1), executions(1)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31   disassembler = new disassembler_t(max_xlen);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdqc";
  65
  66   max_xlen = 64;
  67   state.misa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, state.misa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = "imafdc";
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   state.misa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87   state.misa |= 1L << ('u' - 'a'); // advertise support for user mode
  88
  89   while (*p) {
  90     state.misa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   if (supports_extension('Q') && !supports_extension('D'))
 110     bad_isa_string(str);
 111
 112   if (supports_extension('Q') && max_xlen < 64)
 113     bad_isa_string(str);
 114
 115   max_isa = state.misa;
 116 }
 117
 118 void state_t::reset(reg_t max_isa)
 119 {
 120   memset(this, 0, sizeof(*this));
 121   misa = max_isa;
 122   prv = PRV_M;
 123   pc = DEFAULT_RSTVEC;
 124   load_reservation = -1;
 125   tselect = 0;
 126   for (unsigned int i = 0; i < num_triggers; i++)
 127     mcontrol[i].type = 2;
 128 }
 129
 130 void processor_t::set_debug(bool value)
 131 {
 132   debug = value;
 133   if (ext)
 134     ext->set_debug(value);
 135 }
 136
 137 void processor_t::set_histogram(bool value)
 138 {
 139   histogram_enabled = value;
 140 #ifndef RISCV_ENABLE_HISTOGRAM
 141   if (value) {
 142     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 143     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 144   }
 145 #endif
 146 }
 147
 148 void processor_t::reset()
 149 {
 150   state.reset(max_isa);
 151   state.dcsr.halt = halt_on_reset;
 152   halt_on_reset = false;
 153   set_csr(CSR_MSTATUS, state.mstatus);
 154
 155   if (ext)
 156     ext->reset(); // reset the extension
 157
 158   if (sim)
 159     sim->proc_reset(id);
 160 }
 161
 162 // Count number of contiguous 0 bits starting from the LSB.
 163 static int ctz(reg_t val)
 164 {
 165   int res = 0;
 166   if (val)
 167     while ((val & 1) == 0)
 168       val >>= 1, res++;
 169   return res;
 170 }
 171
 172 void processor_t::take_interrupt(reg_t pending_interrupts)
 173 {
 174   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 175   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 176   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 177
 178   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 179   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 180   // M-ints have highest priority; consider S-ints only if no M-ints pending
 181   if (enabled_interrupts == 0)
 182     enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
 183
 184   if (state.dcsr.cause == 0 && enabled_interrupts) {
 185     // nonstandard interrupts have highest priority
 186     if (enabled_interrupts >> IRQ_M_EXT)
 187       enabled_interrupts = enabled_interrupts >> IRQ_M_EXT << IRQ_M_EXT;
 188     // external interrupts have next-highest priority
 189     else if (enabled_interrupts & (MIP_MEIP | MIP_SEIP))
 190       enabled_interrupts = enabled_interrupts & (MIP_MEIP | MIP_SEIP);
 191     // software interrupts have next-highest priority
 192     else if (enabled_interrupts & (MIP_MSIP | MIP_SSIP))
 193       enabled_interrupts = enabled_interrupts & (MIP_MSIP | MIP_SSIP);
 194     // timer interrupts have next-highest priority
 195     else if (enabled_interrupts & (MIP_MTIP | MIP_STIP))
 196       enabled_interrupts = enabled_interrupts & (MIP_MTIP | MIP_STIP);
 197     else
 198       abort();
 199
 200     throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
 201   }
 202 }
 203
 204 static int xlen_to_uxl(int xlen)
 205 {
 206   if (xlen == 32)
 207     return 1;
 208   if (xlen == 64)
 209     return 2;
 210   abort();
 211 }
 212
 213 reg_t processor_t::legalize_privilege(reg_t prv)
 214 {
 215   assert(prv <= PRV_M);
 216
 217   if (!supports_extension('U'))
 218     return PRV_M;
 219
 220   if (prv == PRV_H || !supports_extension('S'))
 221     return PRV_U;
 222
 223   return prv;
 224 }
 225
 226 void processor_t::set_privilege(reg_t prv)
 227 {
 228   mmu->flush_tlb();
 229   state.prv = legalize_privilege(prv);
 230 }
 231
 232 void processor_t::enter_debug_mode(uint8_t cause)
 233 {
 234   state.dcsr.cause = cause;
 235   state.dcsr.prv = state.prv;
 236   set_privilege(PRV_M);
 237   state.dpc = state.pc;
 238   state.pc = DEBUG_ROM_ENTRY;
 239 }
 240
 241 void processor_t::take_trap(trap_t& t, reg_t epc)
 242 {
 243   if (debug) {
 244     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 245             id, t.name(), epc);
 246     if (t.has_tval())
 247       fprintf(stderr, "core %3d:           tval 0x%016" PRIx64 "\n", id,
 248           t.get_tval());
 249   }
 250
 251   if (state.dcsr.cause) {
 252     if (t.cause() == CAUSE_BREAKPOINT) {
 253       state.pc = DEBUG_ROM_ENTRY;
 254     } else {
 255       state.pc = DEBUG_ROM_TVEC;
 256     }
 257     return;
 258   }
 259
 260   if (t.cause() == CAUSE_BREAKPOINT && (
 261               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 262               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 263               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 264     enter_debug_mode(DCSR_CAUSE_SWBP);
 265     return;
 266   }
 267
 268   // by default, trap to M-mode, unless delegated to S-mode
 269   reg_t bit = t.cause();
 270   reg_t deleg = state.medeleg;
 271   bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
 272   if (interrupt)
 273     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 274   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 275     // handle the trap in S-mode
 276     state.pc = state.stvec;
 277     state.scause = t.cause();
 278     state.sepc = epc;
 279     state.stval = t.get_tval();
 280
 281     reg_t s = state.mstatus;
 282     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
 283     s = set_field(s, MSTATUS_SPP, state.prv);
 284     s = set_field(s, MSTATUS_SIE, 0);
 285     set_csr(CSR_MSTATUS, s);
 286     set_privilege(PRV_S);
 287   } else {
 288     reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0;
 289     state.pc = (state.mtvec & ~(reg_t)1) + vector;
 290     state.mepc = epc;
 291     state.mcause = t.cause();
 292     state.mtval = t.get_tval();
 293
 294     reg_t s = state.mstatus;
 295     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
 296     s = set_field(s, MSTATUS_MPP, state.prv);
 297     s = set_field(s, MSTATUS_MIE, 0);
 298     set_csr(CSR_MSTATUS, s);
 299     set_privilege(PRV_M);
 300   }
 301
 302   yield_load_reservation();
 303 }
 304
 305 void processor_t::disasm(insn_t insn)
 306 {
 307   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 308   if (last_pc != state.pc || last_bits != bits) {
 309     if (executions != 1) {
 310       fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions);
 311     }
 312
 313     fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 314             id, state.pc, bits, disassembler->disassemble(insn).c_str());
 315     last_pc = state.pc;
 316     last_bits = bits;
 317     executions = 1;
 318   } else {
 319     executions++;
 320   }
 321 }
 322
 323 int processor_t::paddr_bits()
 324 {
 325   assert(xlen == max_xlen);
 326   return max_xlen == 64 ? 50 : 34;
 327 }
 328
 329 void processor_t::set_csr(int which, reg_t val)
 330 {
 331   val = zext_xlen(val);
 332   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 333   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 334   switch (which)
 335   {
 336     case CSR_FFLAGS:
 337       dirty_fp_state;
 338       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 339       break;
 340     case CSR_FRM:
 341       dirty_fp_state;
 342       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 343       break;
 344     case CSR_FCSR:
 345       dirty_fp_state;
 346       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 347       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 348       break;
 349     case CSR_MSTATUS: {
 350       if ((val ^ state.mstatus) &
 351           (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
 352         mmu->flush_tlb();
 353
 354       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 355                  | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
 356                  | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
 357                  | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL |
 358                  (ext ? MSTATUS_XS : 0);
 359
 360       reg_t requested_mpp = legalize_privilege(get_field(val, MSTATUS_MPP));
 361       state.mstatus = set_field(state.mstatus, MSTATUS_MPP, requested_mpp);
 362       if (supports_extension('S'))
 363         mask |= MSTATUS_SPP;
 364
 365       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 366
 367       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 368       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 369       if (max_xlen == 32)
 370         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 371       else
 372         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 373
 374       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 375       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 376       state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen));
 377       // U-XLEN == S-XLEN == M-XLEN
 378       xlen = max_xlen;
 379       break;
 380     }
 381     case CSR_MIP: {
 382       reg_t mask = MIP_SSIP | MIP_STIP;
 383       state.mip = (state.mip & ~mask) | (val & mask);
 384       break;
 385     }
 386     case CSR_MIE:
 387       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 388       break;
 389     case CSR_MIDELEG:
 390       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 391       break;
 392     case CSR_MEDELEG: {
 393       reg_t mask =
 394         (1 << CAUSE_MISALIGNED_FETCH) |
 395         (1 << CAUSE_BREAKPOINT) |
 396         (1 << CAUSE_USER_ECALL) |
 397         (1 << CAUSE_FETCH_PAGE_FAULT) |
 398         (1 << CAUSE_LOAD_PAGE_FAULT) |
 399         (1 << CAUSE_STORE_PAGE_FAULT);
 400       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 401       break;
 402     }
 403     case CSR_MINSTRET:
 404     case CSR_MCYCLE:
 405       if (xlen == 32)
 406         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 407       else
 408         state.minstret = val;
 409       break;
 410     case CSR_MINSTRETH:
 411     case CSR_MCYCLEH:
 412       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 413       break;
 414     case CSR_SCOUNTEREN:
 415       state.scounteren = val;
 416       break;
 417     case CSR_MCOUNTEREN:
 418       state.mcounteren = val;
 419       break;
 420     case CSR_SSTATUS: {
 421       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 422                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
 423       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 424     }
 425     case CSR_SIP: {
 426       reg_t mask = MIP_SSIP & state.mideleg;
 427       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
 428     }
 429     case CSR_SIE:
 430       return set_csr(CSR_MIE,
 431                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 432     case CSR_SATP: {
 433       mmu->flush_tlb();
 434       if (max_xlen == 32)
 435         state.satp = val & (SATP32_PPN | SATP32_MODE);
 436       if (max_xlen == 64 && (get_field(val, SATP64_MODE) == SATP_MODE_OFF ||
 437                              get_field(val, SATP64_MODE) == SATP_MODE_SV39 ||
 438                              get_field(val, SATP64_MODE) == SATP_MODE_SV48))
 439         state.satp = val & (SATP64_PPN | SATP64_MODE);
 440       break;
 441     }
 442     case CSR_SEPC: state.sepc = val & ~(reg_t)1; break;
 443     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 444     case CSR_SSCRATCH: state.sscratch = val; break;
 445     case CSR_SCAUSE: state.scause = val; break;
 446     case CSR_STVAL: state.stval = val; break;
 447     case CSR_MEPC: state.mepc = val & ~(reg_t)1; break;
 448     case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
 449     case CSR_MSCRATCH: state.mscratch = val; break;
 450     case CSR_MCAUSE: state.mcause = val; break;
 451     case CSR_MTVAL: state.mtval = val; break;
 452     case CSR_MISA: {
 453       if (!(val & (1L << ('F' - 'A'))))
 454         val &= ~(1L << ('D' - 'A'));
 455
 456       // allow MAFDC bits in MISA to be modified
 457       reg_t mask = 0;
 458       mask |= 1L << ('M' - 'A');
 459       mask |= 1L << ('A' - 'A');
 460       mask |= 1L << ('F' - 'A');
 461       mask |= 1L << ('D' - 'A');
 462       mask |= 1L << ('C' - 'A');
 463       mask &= max_isa;
 464
 465       state.misa = (val & mask) | (state.misa & ~mask);
 466       break;
 467     }
 468     case CSR_TSELECT:
 469       if (val < state.num_triggers) {
 470         state.tselect = val;
 471       }
 472       break;
 473     case CSR_TDATA1:
 474       {
 475         mcontrol_t *mc = &state.mcontrol[state.tselect];
 476         if (mc->dmode && !state.dcsr.cause) {
 477           break;
 478         }
 479         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 480         mc->select = get_field(val, MCONTROL_SELECT);
 481         mc->timing = get_field(val, MCONTROL_TIMING);
 482         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 483         mc->chain = get_field(val, MCONTROL_CHAIN);
 484         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 485         mc->m = get_field(val, MCONTROL_M);
 486         mc->h = get_field(val, MCONTROL_H);
 487         mc->s = get_field(val, MCONTROL_S);
 488         mc->u = get_field(val, MCONTROL_U);
 489         mc->execute = get_field(val, MCONTROL_EXECUTE);
 490         mc->store = get_field(val, MCONTROL_STORE);
 491         mc->load = get_field(val, MCONTROL_LOAD);
 492         // Assume we're here because of csrw.
 493         if (mc->execute)
 494           mc->timing = 0;
 495         trigger_updated();
 496       }
 497       break;
 498     case CSR_TDATA2:
 499       if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
 500         break;
 501       }
 502       if (state.tselect < state.num_triggers) {
 503         state.tdata2[state.tselect] = val;
 504       }
 505       break;
 506     case CSR_DCSR:
 507       state.dcsr.prv = get_field(val, DCSR_PRV);
 508       state.dcsr.step = get_field(val, DCSR_STEP);
 509       // TODO: ndreset and fullreset
 510       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 511       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 512       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 513       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 514       state.dcsr.halt = get_field(val, DCSR_HALT);
 515       break;
 516     case CSR_DPC:
 517       state.dpc = val & ~(reg_t)1;
 518       break;
 519     case CSR_DSCRATCH:
 520       state.dscratch = val;
 521       break;
 522   }
 523 }
 524
 525 reg_t processor_t::get_csr(int which)
 526 {
 527   uint32_t ctr_en = -1;
 528   if (state.prv < PRV_M)
 529     ctr_en &= state.mcounteren;
 530   if (state.prv < PRV_S)
 531     ctr_en &= state.scounteren;
 532   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 533
 534   if (ctr_ok) {
 535     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 536       return 0;
 537     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 538       return 0;
 539   }
 540   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 541     return 0;
 542   if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H)
 543     return 0;
 544   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 545     return 0;
 546
 547   switch (which)
 548   {
 549     case CSR_FFLAGS:
 550       require_fp;
 551       if (!supports_extension('F'))
 552         break;
 553       return state.fflags;
 554     case CSR_FRM:
 555       require_fp;
 556       if (!supports_extension('F'))
 557         break;
 558       return state.frm;
 559     case CSR_FCSR:
 560       require_fp;
 561       if (!supports_extension('F'))
 562         break;
 563       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 564     case CSR_INSTRET:
 565     case CSR_CYCLE:
 566       if (ctr_ok)
 567         return state.minstret;
 568       break;
 569     case CSR_MINSTRET:
 570     case CSR_MCYCLE:
 571       return state.minstret;
 572     case CSR_INSTRETH:
 573     case CSR_CYCLEH:
 574       if (ctr_ok && xlen == 32)
 575         return state.minstret >> 32;
 576       break;
 577     case CSR_MINSTRETH:
 578     case CSR_MCYCLEH:
 579       if (xlen == 32)
 580         return state.minstret >> 32;
 581       break;
 582     case CSR_SCOUNTEREN: return state.scounteren;
 583     case CSR_MCOUNTEREN: return state.mcounteren;
 584     case CSR_SSTATUS: {
 585       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 586                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_UXL;
 587       reg_t sstatus = state.mstatus & mask;
 588       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 589           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 590         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 591       return sstatus;
 592     }
 593     case CSR_SIP: return state.mip & state.mideleg;
 594     case CSR_SIE: return state.mie & state.mideleg;
 595     case CSR_SEPC: return state.sepc;
 596     case CSR_STVAL: return state.stval;
 597     case CSR_STVEC: return state.stvec;
 598     case CSR_SCAUSE:
 599       if (max_xlen > xlen)
 600         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 601       return state.scause;
 602     case CSR_SATP:
 603       if (get_field(state.mstatus, MSTATUS_TVM))
 604         require_privilege(PRV_M);
 605       return state.satp;
 606     case CSR_SSCRATCH: return state.sscratch;
 607     case CSR_MSTATUS: return state.mstatus;
 608     case CSR_MIP: return state.mip;
 609     case CSR_MIE: return state.mie;
 610     case CSR_MEPC: return state.mepc;
 611     case CSR_MSCRATCH: return state.mscratch;
 612     case CSR_MCAUSE: return state.mcause;
 613     case CSR_MTVAL: return state.mtval;
 614     case CSR_MISA: return state.misa;
 615     case CSR_MARCHID: return 0;
 616     case CSR_MIMPID: return 0;
 617     case CSR_MVENDORID: return 0;
 618     case CSR_MHARTID: return id;
 619     case CSR_MTVEC: return state.mtvec;
 620     case CSR_MEDELEG: return state.medeleg;
 621     case CSR_MIDELEG: return state.mideleg;
 622     case CSR_TSELECT: return state.tselect;
 623     case CSR_TDATA1:
 624       if (state.tselect < state.num_triggers) {
 625         reg_t v = 0;
 626         mcontrol_t *mc = &state.mcontrol[state.tselect];
 627         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 628         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 629         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 630         v = set_field(v, MCONTROL_SELECT, mc->select);
 631         v = set_field(v, MCONTROL_TIMING, mc->timing);
 632         v = set_field(v, MCONTROL_ACTION, mc->action);
 633         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 634         v = set_field(v, MCONTROL_MATCH, mc->match);
 635         v = set_field(v, MCONTROL_M, mc->m);
 636         v = set_field(v, MCONTROL_H, mc->h);
 637         v = set_field(v, MCONTROL_S, mc->s);
 638         v = set_field(v, MCONTROL_U, mc->u);
 639         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 640         v = set_field(v, MCONTROL_STORE, mc->store);
 641         v = set_field(v, MCONTROL_LOAD, mc->load);
 642         return v;
 643       } else {
 644         return 0;
 645       }
 646       break;
 647     case CSR_TDATA2:
 648       if (state.tselect < state.num_triggers) {
 649         return state.tdata2[state.tselect];
 650       } else {
 651         return 0;
 652       }
 653       break;
 654     case CSR_TDATA3: return 0;
 655     case CSR_DCSR:
 656       {
 657         uint32_t v = 0;
 658         v = set_field(v, DCSR_XDEBUGVER, 1);
 659         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 660         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 661         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 662         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 663         v = set_field(v, DCSR_STOPCYCLE, 0);
 664         v = set_field(v, DCSR_STOPTIME, 0);
 665         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 666         v = set_field(v, DCSR_STEP, state.dcsr.step);
 667         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 668         return v;
 669       }
 670     case CSR_DPC:
 671       return state.dpc;
 672     case CSR_DSCRATCH:
 673       return state.dscratch;
 674   }
 675   throw trap_illegal_instruction(0);
 676 }
 677
 678 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 679 {
 680   throw trap_illegal_instruction(0);
 681 }
 682
 683 insn_func_t processor_t::decode_insn(insn_t insn)
 684 {
 685   // look up opcode in hash table
 686   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 687   insn_desc_t desc = opcode_cache[idx];
 688
 689   if (unlikely(insn.bits() != desc.match)) {
 690     // fall back to linear search
 691     insn_desc_t* p = &instructions[0];
 692     while ((insn.bits() & p->mask) != p->match)
 693       p++;
 694     desc = *p;
 695
 696     if (p->mask != 0 && p > &instructions[0]) {
 697       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 698         // move to front of opcode list to reduce miss penalty
 699         while (--p >= &instructions[0])
 700           *(p+1) = *p;
 701         instructions[0] = desc;
 702       }
 703     }
 704
 705     opcode_cache[idx] = desc;
 706     opcode_cache[idx].match = insn.bits();
 707   }
 708
 709   return xlen == 64 ? desc.rv64 : desc.rv32;
 710 }
 711
 712 void processor_t::register_insn(insn_desc_t desc)
 713 {
 714   instructions.push_back(desc);
 715 }
 716
 717 void processor_t::build_opcode_map()
 718 {
 719   struct cmp {
 720     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 721       if (lhs.match == rhs.match)
 722         return lhs.mask > rhs.mask;
 723       return lhs.match > rhs.match;
 724     }
 725   };
 726   std::sort(instructions.begin(), instructions.end(), cmp());
 727
 728   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 729     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 730 }
 731
 732 void processor_t::register_extension(extension_t* x)
 733 {
 734   for (auto insn : x->get_instructions())
 735     register_insn(insn);
 736   build_opcode_map();
 737   for (auto disasm_insn : x->get_disasms())
 738     disassembler->add_insn(disasm_insn);
 739   if (ext != NULL)
 740     throw std::logic_error("only one extension may be registered");
 741   ext = x;
 742   x->set_processor(this);
 743 }
 744
 745 void processor_t::register_base_instructions()
 746 {
 747   #define DECLARE_INSN(name, match, mask) \
 748     insn_bits_t name##_match = (match), name##_mask = (mask);
 749   #include "encoding.h"
 750   #undef DECLARE_INSN
 751
 752   #define DEFINE_INSN(name) \
 753     REGISTER_INSN(this, name, name##_match, name##_mask)
 754   #include "insn_list.h"
 755   #undef DEFINE_INSN
 756
 757   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 758   build_opcode_map();
 759 }
 760
 761 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 762 {
 763   switch (addr)
 764   {
 765     case 0:
 766       if (len <= 4) {
 767         memset(bytes, 0, len);
 768         bytes[0] = get_field(state.mip, MIP_MSIP);
 769         return true;
 770       }
 771       break;
 772   }
 773
 774   return false;
 775 }
 776
 777 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 778 {
 779   switch (addr)
 780   {
 781     case 0:
 782       if (len <= 4) {
 783         state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
 784         return true;
 785       }
 786       break;
 787   }
 788
 789   return false;
 790 }
 791
 792 void processor_t::trigger_updated()
 793 {
 794   mmu->flush_tlb();
 795   mmu->check_triggers_fetch = false;
 796   mmu->check_triggers_load = false;
 797   mmu->check_triggers_store = false;
 798
 799   for (unsigned i = 0; i < state.num_triggers; i++) {
 800     if (state.mcontrol[i].execute) {
 801       mmu->check_triggers_fetch = true;
 802     }
 803     if (state.mcontrol[i].load) {
 804       mmu->check_triggers_load = true;
 805     }
 806     if (state.mcontrol[i].store) {
 807       mmu->check_triggers_store = true;
 808     }
 809   }
 810 }