riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "disasm.h"
   9 #include <cinttypes>
  10 #include <cmath>
  11 #include <cstdlib>
  12 #include <iostream>
  13 #include <assert.h>
  14 #include <limits.h>
  15 #include <stdexcept>
  16
  17 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
  18   : sim(_sim), mmu(_mmu), ext(NULL), id(_id), opcode_bits(0)
  19 {
  20   reset(true);
  21   mmu->set_processor(this);
  22
  23   #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
  24   #include "opcodes.h"
  25   #undef DECLARE_INSN
  26 }
  27
  28 processor_t::~processor_t()
  29 {
  30 }
  31
  32 void state_t::reset()
  33 {
  34   // the ISA guarantees on boot that the PC is 0x2000 and the the processor
  35   // is in supervisor mode, and in 64-bit mode, if supported, with traps
  36   // and virtual memory disabled.
  37   sr = SR_S;
  38 #ifdef RISCV_ENABLE_64BIT
  39   sr |= SR_S64;
  40 #endif
  41   pc = 0x2000;
  42
  43   // the following state is undefined upon boot-up,
  44   // but we zero it for determinism
  45   XPR.reset();
  46   FPR.reset();
  47
  48   evec = 0;
  49   epc = 0;
  50   badvaddr = 0;
  51   cause = 0;
  52   pcr_k0 = 0;
  53   pcr_k1 = 0;
  54   count = 0;
  55   compare = 0;
  56   cycle = 0;
  57   fsr = 0;
  58
  59   load_reservation = -1;
  60 }
  61
  62 void processor_t::reset(bool value)
  63 {
  64   if (run == !value)
  65     return;
  66   run = !value;
  67
  68   state.reset();
  69 }
  70
  71 uint32_t processor_t::set_fsr(uint32_t val)
  72 {
  73   uint32_t old_fsr = state.fsr;
  74   state.fsr = val & ~FSR_ZERO; // clear FSR bits that read as zero
  75   return old_fsr;
  76 }
  77
  78 void processor_t::take_interrupt()
  79 {
  80   uint32_t interrupts = (state.sr & SR_IP) >> SR_IP_SHIFT;
  81   interrupts &= (state.sr & SR_IM) >> SR_IM_SHIFT;
  82
  83   if (interrupts && (state.sr & SR_EI))
  84     for (int i = 0; ; i++, interrupts >>= 1)
  85       if (interrupts & 1)
  86         throw trap_t((1ULL << ((state.sr & SR_S64) ? 63 : 31)) + i);
  87 }
  88
  89 void processor_t::step(size_t n, bool noisy)
  90 {
  91   if(!run)
  92     return;
  93
  94   size_t i = 0;
  95   reg_t npc = state.pc;
  96   mmu_t* _mmu = mmu;
  97
  98   try
  99   {
 100     take_interrupt();
 101
 102     // execute_insn fetches and executes one instruction
 103     #define execute_insn(noisy) \
 104       do { \
 105         mmu_t::insn_fetch_t fetch = _mmu->load_insn(npc); \
 106         if(noisy) disasm(fetch.insn.insn, npc); \
 107         npc = fetch.func(this, fetch.insn.insn, npc); \
 108       } while(0)
 109
 110     if(noisy) for( ; i < n; i++) // print out instructions as we go
 111       execute_insn(true);
 112     else
 113     {
 114       // unrolled for speed
 115       for( ; n > 3 && i < n-3; i+=4)
 116       {
 117         execute_insn(false);
 118         execute_insn(false);
 119         execute_insn(false);
 120         execute_insn(false);
 121       }
 122       for( ; i < n; i++)
 123         execute_insn(false);
 124     }
 125
 126     state.pc = npc;
 127   }
 128   catch(trap_t& t)
 129   {
 130     take_trap(npc, t, noisy);
 131   }
 132
 133   state.cycle += i;
 134
 135   // update timer and possibly register a timer interrupt
 136   uint32_t old_count = state.count;
 137   state.count += i;
 138   if(old_count < state.compare && uint64_t(old_count) + i >= state.compare)
 139     set_interrupt(IRQ_TIMER, true);
 140 }
 141
 142 void processor_t::take_trap(reg_t pc, trap_t& t, bool noisy)
 143 {
 144   if (noisy)
 145     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 146             id, t.name(), pc);
 147
 148   // switch to supervisor, set previous supervisor bit, disable interrupts
 149   set_pcr(PCR_SR, (((state.sr & ~SR_EI) | SR_S) & ~SR_PS & ~SR_PEI) |
 150                   ((state.sr & SR_S) ? SR_PS : 0) |
 151                   ((state.sr & SR_EI) ? SR_PEI : 0));
 152
 153   yield_load_reservation();
 154   state.cause = t.cause();
 155   state.epc = pc;
 156   state.pc = state.evec;
 157
 158   t.side_effects(&state); // might set badvaddr etc.
 159 }
 160
 161 void processor_t::deliver_ipi()
 162 {
 163   if (run)
 164     set_pcr(PCR_CLR_IPI, 1);
 165 }
 166
 167 void processor_t::disasm(insn_t insn, reg_t pc)
 168 {
 169   // the disassembler is stateless, so we share it
 170   static disassembler disasm;
 171   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n",
 172           id, state.pc, insn.bits(), disasm.disassemble(insn).c_str());
 173 }
 174
 175 reg_t processor_t::set_pcr(int which, reg_t val)
 176 {
 177   reg_t old_pcr = get_pcr(which);
 178
 179   switch (which)
 180   {
 181     case PCR_SR:
 182       state.sr = (val & ~SR_IP) | (state.sr & SR_IP);
 183 #ifndef RISCV_ENABLE_64BIT
 184       state.sr &= ~(SR_S64 | SR_U64);
 185 #endif
 186 #ifndef RISCV_ENABLE_FPU
 187       state.sr &= ~SR_EF;
 188 #endif
 189 #ifndef RISCV_ENABLE_VEC
 190       state.sr &= ~SR_EV;
 191 #endif
 192       state.sr &= ~SR_ZERO;
 193       mmu->flush_tlb();
 194       break;
 195     case PCR_EPC:
 196       state.epc = val;
 197       break;
 198     case PCR_EVEC:
 199       state.evec = val;
 200       break;
 201     case PCR_COUNT:
 202       state.count = val;
 203       break;
 204     case PCR_COMPARE:
 205       set_interrupt(IRQ_TIMER, false);
 206       state.compare = val;
 207       break;
 208     case PCR_PTBR:
 209       state.ptbr = val & ~(PGSIZE-1);
 210       break;
 211     case PCR_SEND_IPI:
 212       sim->send_ipi(val);
 213       break;
 214     case PCR_CLR_IPI:
 215       set_interrupt(IRQ_IPI, val & 1);
 216       break;
 217     case PCR_SUP0:
 218       state.pcr_k0 = val;
 219       break;
 220     case PCR_SUP1:
 221       state.pcr_k1 = val;
 222       break;
 223     case PCR_TOHOST:
 224       if (state.tohost == 0)
 225         state.tohost = val;
 226       break;
 227     case PCR_FROMHOST:
 228       set_interrupt(IRQ_HOST, val != 0);
 229       state.fromhost = val;
 230       break;
 231   }
 232
 233   return old_pcr;
 234 }
 235
 236 reg_t processor_t::get_pcr(int which)
 237 {
 238   switch (which)
 239   {
 240     case PCR_SR:
 241       return state.sr;
 242     case PCR_EPC:
 243       return state.epc;
 244     case PCR_BADVADDR:
 245       return state.badvaddr;
 246     case PCR_EVEC:
 247       return state.evec;
 248     case PCR_COUNT:
 249       return state.count;
 250     case PCR_COMPARE:
 251       return state.compare;
 252     case PCR_CAUSE:
 253       return state.cause;
 254     case PCR_PTBR:
 255       return state.ptbr;
 256     case PCR_ASID:
 257       return 0;
 258     case PCR_FATC:
 259       mmu->flush_tlb();
 260       return 0;
 261     case PCR_HARTID:
 262       return id;
 263     case PCR_IMPL:
 264       return 1;
 265     case PCR_SUP0:
 266       return state.pcr_k0;
 267     case PCR_SUP1:
 268       return state.pcr_k1;
 269     case PCR_TOHOST:
 270       return state.tohost;
 271     case PCR_FROMHOST:
 272       return state.fromhost;
 273   }
 274   return -1;
 275 }
 276
 277 void processor_t::set_interrupt(int which, bool on)
 278 {
 279   uint32_t mask = (1 << (which + SR_IP_SHIFT)) & SR_IP;
 280   if (on)
 281     state.sr |= mask;
 282   else
 283     state.sr &= ~mask;
 284 }
 285
 286 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 287 {
 288   throw trap_illegal_instruction();
 289 }
 290
 291 insn_func_t processor_t::decode_insn(insn_t insn)
 292 {
 293   bool rv64 = (state.sr & SR_S) ? (state.sr & SR_S64) : (state.sr & SR_U64);
 294
 295   auto key = insn.bits() & ((1L << opcode_bits)-1);
 296   for (auto it = opcode_map.find(key); it != opcode_map.end() && it->first == key; ++it)
 297     if ((insn.bits() & it->second.mask) == it->second.match)
 298       return rv64 ? it->second.rv64 : it->second.rv32;
 299
 300   return &illegal_instruction;
 301 }
 302
 303 void processor_t::register_insn(insn_desc_t desc)
 304 {
 305   assert(desc.mask & 1);
 306   if (opcode_bits == 0 || (desc.mask & ((1L << opcode_bits)-1)) != ((1L << opcode_bits)-1))
 307   {
 308     unsigned x = 0;
 309     while ((desc.mask & ((1L << (x+1))-1)) == ((1L << (x+1))-1) &&
 310            (opcode_bits == 0 || x <= opcode_bits))
 311       x++;
 312     opcode_bits = x;
 313
 314     decltype(opcode_map) new_map;
 315     for (auto it = opcode_map.begin(); it != opcode_map.end(); ++it)
 316       new_map.insert(std::make_pair(it->second.match & ((1L<<x)-1), it->second));
 317     opcode_map = new_map;
 318   }
 319
 320   opcode_map.insert(std::make_pair(desc.match & ((1L<<opcode_bits)-1), desc));
 321 }
 322
 323 void processor_t::register_extension(extension_t* x)
 324 {
 325   for (auto insn : x->get_instructions())
 326     register_insn(insn);
 327   if (ext != NULL)
 328     throw std::logic_error("only one extension may be registered");
 329   ext = x;
 330   x->set_processor(this);
 331 }