9f87f75c0300779d52390d120a41e2285e3cff3f
12 processor_t::processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
)
13 : sim(*_sim
), mmu(*_mmu
), id(_id
), utidx(0)
17 // create microthreads
18 for (int i
=0; i
<MAX_UTS
; i
++)
19 uts
[i
] = new processor_t(&sim
, &mmu
, id
, i
);
22 processor_t::processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
,
24 : sim(*_sim
), mmu(*_mmu
), id(_id
)
27 set_pcr(PCR_SR
, SR_U64
| SR_EF
| SR_EV
);
30 // microthreads don't possess their own microthreads
31 for (int i
=0; i
<MAX_UTS
; i
++)
35 processor_t::~processor_t()
39 void processor_t::reset(bool value
)
45 // the ISA guarantees on boot that the PC is 0x2000 and the the processor
46 // is in supervisor mode, and in 64-bit mode, if supported, with traps
47 // and virtual memory disabled.
48 set_pcr(PCR_SR
, SR_S
| SR_S64
| SR_IM
);
51 // the following state is undefined upon boot-up,
52 // but we zero it for determinism
78 void processor_t::set_fsr(uint32_t val
)
80 fsr
= val
& ~FSR_ZERO
; // clear FSR bits that read as zero
83 void processor_t::vcfg()
85 if (nxpr_use
+ nfpr_use
< 2)
86 vlmax
= nxfpr_bank
* vecbanks_count
;
88 vlmax
= (nxfpr_bank
/ (nxpr_use
+ nfpr_use
- 1)) * vecbanks_count
;
90 vlmax
= std::min(vlmax
, MAX_UTS
);
93 void processor_t::setvl(int vlapp
)
95 vl
= std::min(vlmax
, vlapp
);
98 void processor_t::take_interrupt()
100 uint32_t interrupts
= (sr
& SR_IP
) >> SR_IP_SHIFT
;
101 interrupts
&= (sr
& SR_IM
) >> SR_IM_SHIFT
;
103 if(interrupts
&& (sr
& SR_ET
))
104 for(int i
= 0; ; i
++, interrupts
>>= 1)
106 throw interrupt_t(i
);
109 void processor_t::step(size_t n
, bool noisy
)
122 // execute_insn fetches and executes one instruction
123 #define execute_insn(noisy) \
125 mmu_t::insn_fetch_t fetch = _mmu.load_insn(npc, sr & SR_EC); \
126 if(noisy) disasm(fetch.insn, npc); \
127 npc = fetch.func(this, fetch.insn, npc); \
131 if(noisy
) for( ; i
< n
; i
++) // print out instructions as we go
135 // unrolled for speed
136 for( ; n
> 3 && i
< n
-3; i
+=4)
149 // an exception occurred in the target processor
154 take_trap((1ULL << (8*sizeof(reg_t
)-1)) + t
.i
, noisy
);
156 catch(vt_command_t cmd
)
158 // this microthread has finished
159 assert(cmd
== vt_command_stop
);
164 // update timer and possibly register a timer interrupt
165 uint32_t old_count
= count
;
167 if(old_count
< compare
&& uint64_t(old_count
) + i
>= compare
)
168 set_interrupt(IRQ_TIMER
, true);
171 void processor_t::take_trap(reg_t t
, bool noisy
)
176 printf("core %3d: interrupt %lld, pc 0x%016llx\n",
177 id
, (long long)(t
<< 1 >> 1), (unsigned long long)pc
);
179 printf("core %3d: trap %s, pc 0x%016llx\n",
180 id
, trap_name(trap_t(t
)), (unsigned long long)pc
);
183 // switch to supervisor, set previous supervisor bit, disable traps
184 set_pcr(PCR_SR
, (((sr
& ~SR_ET
) | SR_S
) & ~SR_PS
) | ((sr
& SR_S
) ? SR_PS
: 0));
188 badvaddr
= mmu
.get_badvaddr();
191 void processor_t::deliver_ipi()
194 set_pcr(PCR_CLR_IPI
, 1);
197 void processor_t::disasm(insn_t insn
, reg_t pc
)
199 // the disassembler is stateless, so we share it
200 static disassembler disasm
;
201 printf("core %3d: 0x%016llx (0x%08x) %s\n", id
, (unsigned long long)pc
,
202 insn
.bits
, disasm
.disassemble(insn
).c_str());
205 void processor_t::set_pcr(int which
, reg_t val
)
210 sr
= val
& ~SR_ZERO
; // clear SR bits that read as zero
211 #ifndef RISCV_ENABLE_64BIT
212 sr
&= ~(SR_S64
| SR_U64
);
214 #ifndef RISCV_ENABLE_FPU
217 #ifndef RISCV_ENABLE_RVC
220 #ifndef RISCV_ENABLE_VEC
223 // update MMU state and flush TLB
226 // set the fixed-point register length
227 xprlen
= ((sr
& SR_S
) ? (sr
& SR_S64
) : (sr
& SR_U64
)) ? 64 : 32;
239 set_interrupt(IRQ_TIMER
, false);
249 set_interrupt(IRQ_IPI
, val
& 1);
258 vecbanks
= val
& 0xff;
259 vecbanks_count
= __builtin_popcountll(vecbanks
);
266 set_interrupt(IRQ_HOST
, val
!= 0);
272 reg_t
processor_t::get_pcr(int which
)
291 return mmu
.get_ptbr();
310 void processor_t::set_interrupt(int which
, bool on
)
312 uint32_t mask
= (1 << (which
+ SR_IP_SHIFT
)) & SR_IP
;