riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "htif.h"
   9 #include "disasm.h"
  10 #include "icache.h"
  11 #include <cinttypes>
  12 #include <cmath>
  13 #include <cstdlib>
  14 #include <iostream>
  15 #include <assert.h>
  16 #include <limits.h>
  17 #include <stdexcept>
  18 #include <algorithm>
  19
  20 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
  21   : sim(_sim), mmu(_mmu), ext(NULL), disassembler(new disassembler_t),
  22     id(_id), run(false), debug(false)
  23 {
  24   reset(true);
  25   mmu->set_processor(this);
  26
  27   #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
  28   #include "encoding.h"
  29   #undef DECLARE_INSN
  30   build_opcode_map();
  31 }
  32
  33 processor_t::~processor_t()
  34 {
  35   delete disassembler;
  36 }
  37
  38 void state_t::reset()
  39 {
  40   // the ISA guarantees on boot that the PC is 0x2000 and the the processor
  41   // is in supervisor mode, and in 64-bit mode, if supported, with traps
  42   // and virtual memory disabled.
  43   sr = SR_S | SR_S64 | SR_U64;
  44   pc = 0x2000;
  45
  46   // the following state is undefined upon boot-up,
  47   // but we zero it for determinism
  48   XPR.reset();
  49   FPR.reset();
  50
  51   epc = 0;
  52   badvaddr = 0;
  53   evec = 0;
  54   ptbr = 0;
  55   pcr_k0 = 0;
  56   pcr_k1 = 0;
  57   cause = 0;
  58   tohost = 0;
  59   fromhost = 0;
  60   count = 0;
  61   compare = 0;
  62   fflags = 0;
  63   frm = 0;
  64
  65   load_reservation = -1;
  66 }
  67
  68 void processor_t::set_debug(bool value)
  69 {
  70   debug = value;
  71   if (ext)
  72     ext->set_debug(value);
  73 }
  74
  75 void processor_t::reset(bool value)
  76 {
  77   if (run == !value)
  78     return;
  79   run = !value;
  80
  81   state.reset(); // reset the core
  82   set_pcr(CSR_STATUS, state.sr);
  83
  84   if (ext)
  85     ext->reset(); // reset the extension
  86 }
  87
  88 void processor_t::take_interrupt()
  89 {
  90   uint32_t interrupts = (state.sr & SR_IP) >> SR_IP_SHIFT;
  91   interrupts &= (state.sr & SR_IM) >> SR_IM_SHIFT;
  92
  93   if (interrupts && (state.sr & SR_EI))
  94     for (int i = 0; ; i++, interrupts >>= 1)
  95       if (interrupts & 1)
  96         throw trap_t((1ULL << ((state.sr & SR_S64) ? 63 : 31)) + i);
  97 }
  98
  99 static void commit_log(state_t* state, insn_t insn)
 100 {
 101 #ifdef RISCV_ENABLE_COMMITLOG
 102   if (!(state->sr & SR_S)) {
 103     fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") ", state->pc, insn.bits());
 104     if (state->log_reg_write.addr)
 105       fprintf(stderr, "%c%02u 0x%016" PRIx64, state->log_reg_write.addr & 1 ? 'f' : 'x',
 106               state->log_reg_write.addr >> 1, state->log_reg_write.data);
 107     state->log_reg_write.addr = 0;
 108   }
 109 #endif
 110 }
 111
 112 void processor_t::step(size_t n)
 113 {
 114   if(!run)
 115     return;
 116
 117   mmu_t* _mmu = mmu;
 118   auto count32 = decltype(state.compare)(state.count);
 119   bool count_le_compare = count32 <= state.compare;
 120   n = std::min(n, size_t(state.compare - count32) | 1);
 121
 122   try
 123   {
 124     take_interrupt();
 125
 126     if (debug) // print out instructions as we go
 127     {
 128       for (size_t i = 0; i < n; state.count++, i++)
 129       {
 130         insn_fetch_t fetch = mmu->load_insn(state.pc);
 131         disasm(fetch.insn.insn);
 132         commit_log(&state, fetch.insn.insn);
 133         state.pc = fetch.func(this, fetch.insn.insn, state.pc);
 134       }
 135     }
 136     else while (n > 0)
 137     {
 138       size_t idx = (state.pc / sizeof(insn_t)) % ICACHE_SIZE;
 139       auto ic_entry = _mmu->access_icache(state.pc), ic_entry_init = ic_entry;
 140
 141       #define ICACHE_ACCESS(idx) { \
 142         insn_t insn = ic_entry->data.insn.insn; \
 143         insn_func_t func = ic_entry->data.func; \
 144         ic_entry++; \
 145         reg_t pc = func(this, insn, state.pc); \
 146         commit_log(&state, insn); \
 147         state.pc = pc; \
 148         if (idx < ICACHE_SIZE-1 && unlikely(ic_entry->tag != state.pc)) break; \
 149       }
 150
 151       switch (idx)
 152       {
 153         ICACHE_SWITCH; // auto-generated into icache.h
 154       }
 155
 156       size_t i = ic_entry - ic_entry_init;
 157       state.count += i;
 158       if (i >= n)
 159         break;
 160       n -= i;
 161     }
 162   }
 163   catch(trap_t& t)
 164   {
 165     take_trap(t);
 166   }
 167
 168   bool count_ge_compare =
 169     uint64_t(n) + decltype(state.compare)(state.count) >= state.compare;
 170   if (count_le_compare && count_ge_compare)
 171     set_interrupt(IRQ_TIMER, true);
 172 }
 173
 174 void processor_t::take_trap(trap_t& t)
 175 {
 176   if (debug)
 177     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 178             id, t.name(), state.pc);
 179
 180   // switch to supervisor, set previous supervisor bit, disable interrupts
 181   set_pcr(CSR_STATUS, (((state.sr & ~SR_EI) | SR_S) & ~SR_PS & ~SR_PEI) |
 182                       ((state.sr & SR_S) ? SR_PS : 0) |
 183                       ((state.sr & SR_EI) ? SR_PEI : 0));
 184
 185   yield_load_reservation();
 186   state.cause = t.cause();
 187   state.epc = state.pc;
 188   state.pc = state.evec;
 189
 190   t.side_effects(&state); // might set badvaddr etc.
 191 }
 192
 193 void processor_t::deliver_ipi()
 194 {
 195   if (run)
 196     set_pcr(CSR_CLEAR_IPI, 1);
 197 }
 198
 199 void processor_t::disasm(insn_t insn)
 200 {
 201   // the disassembler is stateless, so we share it
 202   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n",
 203           id, state.pc, insn.bits(), disassembler->disassemble(insn).c_str());
 204 }
 205
 206 reg_t processor_t::set_pcr(int which, reg_t val)
 207 {
 208   reg_t old_pcr = get_pcr(which);
 209
 210   switch (which)
 211   {
 212     case CSR_FFLAGS:
 213       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 214       break;
 215     case CSR_FRM:
 216       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 217       break;
 218     case CSR_FCSR:
 219       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 220       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 221       break;
 222     case CSR_STATUS:
 223       state.sr = (val & ~SR_IP) | (state.sr & SR_IP);
 224 #ifndef RISCV_ENABLE_64BIT
 225       state.sr &= ~(SR_S64 | SR_U64);
 226 #endif
 227 #ifndef RISCV_ENABLE_FPU
 228       state.sr &= ~SR_EF;
 229 #endif
 230       if (!ext)
 231         state.sr &= ~SR_EA;
 232       state.sr &= ~SR_ZERO;
 233       rv64 = (state.sr & SR_S) ? (state.sr & SR_S64) : (state.sr & SR_U64);
 234       mmu->flush_tlb();
 235       break;
 236     case CSR_EPC:
 237       state.epc = val;
 238       break;
 239     case CSR_EVEC:
 240       state.evec = val & ~3;
 241       break;
 242     case CSR_COUNT:
 243       state.count = val;
 244       break;
 245     case CSR_COUNTH:
 246       state.count = (val << 32) | (uint32_t)state.count;
 247       break;
 248     case CSR_COMPARE:
 249       set_interrupt(IRQ_TIMER, false);
 250       state.compare = val;
 251       break;
 252     case CSR_PTBR:
 253       state.ptbr = val & ~(PGSIZE-1);
 254       break;
 255     case CSR_SEND_IPI:
 256       sim->send_ipi(val);
 257       break;
 258     case CSR_CLEAR_IPI:
 259       set_interrupt(IRQ_IPI, val & 1);
 260       break;
 261     case CSR_SUP0:
 262       state.pcr_k0 = val;
 263       break;
 264     case CSR_SUP1:
 265       state.pcr_k1 = val;
 266       break;
 267     case CSR_TOHOST:
 268       if (state.tohost == 0)
 269         state.tohost = val;
 270       break;
 271     case CSR_FROMHOST:
 272       set_fromhost(val);
 273       break;
 274   }
 275
 276   return old_pcr;
 277 }
 278
 279 void processor_t::set_fromhost(reg_t val)
 280 {
 281   set_interrupt(IRQ_HOST, val != 0);
 282   state.fromhost = val;
 283 }
 284
 285 reg_t processor_t::get_pcr(int which)
 286 {
 287   switch (which)
 288   {
 289     case CSR_FFLAGS:
 290       return state.fflags;
 291     case CSR_FRM:
 292       return state.frm;
 293     case CSR_FCSR:
 294       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 295     case CSR_STATUS:
 296       return state.sr;
 297     case CSR_EPC:
 298       return state.epc;
 299     case CSR_BADVADDR:
 300       return state.badvaddr;
 301     case CSR_EVEC:
 302       return state.evec;
 303     case CSR_CYCLE:
 304     case CSR_TIME:
 305     case CSR_INSTRET:
 306     case CSR_COUNT:
 307       return state.count;
 308     case CSR_CYCLEH:
 309     case CSR_TIMEH:
 310     case CSR_INSTRETH:
 311     case CSR_COUNTH:
 312       if (rv64)
 313         break;
 314       return state.count >> 32;
 315     case CSR_COMPARE:
 316       return state.compare;
 317     case CSR_CAUSE:
 318       return state.cause;
 319     case CSR_PTBR:
 320       return state.ptbr;
 321     case CSR_SEND_IPI:
 322     case CSR_CLEAR_IPI:
 323       return 0;
 324     case CSR_ASID:
 325       return 0;
 326     case CSR_FATC:
 327       mmu->flush_tlb();
 328       return 0;
 329     case CSR_HARTID:
 330       return id;
 331     case CSR_IMPL:
 332       return 1;
 333     case CSR_SUP0:
 334       return state.pcr_k0;
 335     case CSR_SUP1:
 336       return state.pcr_k1;
 337     case CSR_TOHOST:
 338       sim->get_htif()->tick(); // not necessary, but faster
 339       return state.tohost;
 340     case CSR_FROMHOST:
 341       sim->get_htif()->tick(); // not necessary, but faster
 342       return state.fromhost;
 343   }
 344   throw trap_illegal_instruction();
 345 }
 346
 347 void processor_t::set_interrupt(int which, bool on)
 348 {
 349   uint32_t mask = (1 << (which + SR_IP_SHIFT)) & SR_IP;
 350   if (on)
 351     state.sr |= mask;
 352   else
 353     state.sr &= ~mask;
 354 }
 355
 356 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 357 {
 358   throw trap_illegal_instruction();
 359 }
 360
 361 insn_func_t processor_t::decode_insn(insn_t insn)
 362 {
 363   size_t mask = opcode_map.size()-1;
 364   insn_desc_t* desc = opcode_map[insn.bits() & mask];
 365
 366   while ((insn.bits() & desc->mask) != desc->match)
 367     desc++;
 368
 369   return rv64 ? desc->rv64 : desc->rv32;
 370 }
 371
 372 void processor_t::register_insn(insn_desc_t desc)
 373 {
 374   assert(desc.mask & 1);
 375   instructions.push_back(desc);
 376 }
 377
 378 void processor_t::build_opcode_map()
 379 {
 380   size_t buckets = -1;
 381   for (auto& inst : instructions)
 382     while ((inst.mask & buckets) != buckets)
 383       buckets /= 2;
 384   buckets++;
 385
 386   struct cmp {
 387     decltype(insn_desc_t::match) mask;
 388     cmp(decltype(mask) mask) : mask(mask) {}
 389     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 390       if ((lhs.match & mask) != (rhs.match & mask))
 391         return (lhs.match & mask) < (rhs.match & mask);
 392       return lhs.match < rhs.match;
 393     }
 394   };
 395   std::sort(instructions.begin(), instructions.end(), cmp(buckets-1));
 396
 397   opcode_map.resize(buckets);
 398   opcode_store.resize(instructions.size() + 1);
 399
 400   size_t j = 0;
 401   for (size_t b = 0, i = 0; b < buckets; b++)
 402   {
 403     opcode_map[b] = &opcode_store[j];
 404     while (i < instructions.size() && b == (instructions[i].match & (buckets-1)))
 405       opcode_store[j++] = instructions[i++];
 406   }
 407
 408   assert(j == opcode_store.size()-1);
 409   opcode_store[j].match = opcode_store[j].mask = 0;
 410   opcode_store[j].rv32 = &illegal_instruction;
 411   opcode_store[j].rv64 = &illegal_instruction;
 412 }
 413
 414 void processor_t::register_extension(extension_t* x)
 415 {
 416   for (auto insn : x->get_instructions())
 417     register_insn(insn);
 418   build_opcode_map();
 419   for (auto disasm_insn : x->get_disasms())
 420     disassembler->add_insn(disasm_insn);
 421   if (ext != NULL)
 422     throw std::logic_error("only one extension may be registered");
 423   ext = x;
 424   x->set_processor(this);
 425 }