riscv/riscv-isa-run.cc

   1 #include "sim.h"
   2 #include "htif.h"
   3 #include "cachesim.h"
   4 #include <fesvr/option_parser.h>
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <getopt.h>
   8 #include <vector>
   9 #include <string>
  10 #include <memory>
  11
  12 static void help()
  13 {
  14   fprintf(stderr, "usage: riscv-isa-run [host options] <target program> [target options]\n");
  15   fprintf(stderr, "Host Options:\n");
  16   fprintf(stderr, "  -p <n>             Simulate <n> processors\n");
  17   fprintf(stderr, "  -m <n>             Provide <n> MB of target memory\n");
  18   fprintf(stderr, "  -d                 Interactive debug mode\n");
  19   fprintf(stderr, "  -h                 Print this help message\n");
  20   fprintf(stderr, "  -h                 Print this help message\n");
  21   fprintf(stderr, "  --ic=<S>:<W>:<B>   Instantiate a cache model with S sets,\n");
  22   fprintf(stderr, "  --dc=<S>:<W>:<B>     W ways, and B-byte blocks (with S and\n");
  23   fprintf(stderr, "  --l2=<S>:<W>:<B>     B both powers of 2).\n");
  24   exit(1);
  25 }
  26
  27 int main(int argc, char** argv)
  28 {
  29   bool debug = false;
  30   size_t nprocs = 1;
  31   size_t mem_mb = 0;
  32   std::unique_ptr<icache_sim_t> ic;
  33   std::unique_ptr<dcache_sim_t> dc;
  34   std::unique_ptr<cache_sim_t> l2;
  35
  36   option_parser_t parser;
  37   parser.help(&help);
  38   parser.option('d', 0, 0, [&](const char* s){debug = true;});
  39   parser.option('p', 0, 1, [&](const char* s){nprocs = atoi(s);});
  40   parser.option('m', 0, 1, [&](const char* s){mem_mb = atoi(s);});
  41   parser.option(0, "ic", 1, [&](const char* s){ic.reset(new icache_sim_t(s));});
  42   parser.option(0, "dc", 1, [&](const char* s){dc.reset(new dcache_sim_t(s));});
  43   parser.option(0, "l2", 1, [&](const char* s){l2.reset(cache_sim_t::construct(s, "L2$"));});
  44
  45   auto argv1 = parser.parse(argv);
  46   if (!*argv1)
  47     help();
  48   std::vector<std::string> htif_args(argv1, (const char*const*)argv + argc);
  49   sim_t s(nprocs, mem_mb, htif_args);
  50
  51   if (ic && l2) ic->set_miss_handler(&*l2);
  52   if (dc && l2) dc->set_miss_handler(&*l2);
  53   for (size_t i = 0; i < nprocs; i++)
  54   {
  55     if (ic) s.get_core(i)->get_mmu()->register_memtracer(&*ic);
  56     if (dc) s.get_core(i)->get_mmu()->register_memtracer(&*dc);
  57   }
  58
  59   s.run(debug);
  60 }