59c4f0ed19fab07e697c7981827b0daa38a2e11a
1 // See LICENSE for license details.
15 #include <sys/types.h>
17 volatile bool ctrlc_pressed
= false;
18 static void handle_signal(int sig
)
23 signal(sig
, &handle_signal
);
26 sim_t::sim_t(const char* isa
, size_t nprocs
, bool halted
, reg_t start_pc
,
27 std::vector
<std::pair
<reg_t
, mem_t
*>> mems
,
28 const std::vector
<std::string
>& args
)
29 : htif_t(args
), mems(mems
), procs(std::max(nprocs
, size_t(1))),
31 current_step(0), current_proc(0), debug(false), gdbserver(NULL
)
33 signal(SIGINT
, &handle_signal
);
36 bus
.add_device(x
.first
, x
.second
);
38 bus
.add_device(DEBUG_START
, &debug_module
);
40 debug_mmu
= new mmu_t(this, NULL
);
42 for (size_t i
= 0; i
< procs
.size(); i
++) {
43 procs
[i
] = new processor_t(isa
, this, i
, halted
);
46 clint
.reset(new clint_t(procs
));
47 bus
.add_device(CLINT_BASE
, clint
.get());
54 for (size_t i
= 0; i
< procs
.size(); i
++)
59 void sim_thread_main(void* arg
)
61 ((sim_t
*)arg
)->main();
67 set_procs_debug(true);
71 if (debug
|| ctrlc_pressed
)
83 host
= context_t::current();
84 target
.init(sim_thread_main
, this);
88 void sim_t::step(size_t n
)
90 for (size_t i
= 0, steps
= 0; i
< n
; i
+= steps
)
92 steps
= std::min(n
- i
, INTERLEAVE
- current_step
);
93 procs
[current_proc
]->step(steps
);
95 current_step
+= steps
;
96 if (current_step
== INTERLEAVE
)
99 procs
[current_proc
]->yield_load_reservation();
100 if (++current_proc
== procs
.size()) {
102 clint
->increment(INTERLEAVE
/ INSNS_PER_RTC_TICK
);
110 void sim_t::set_debug(bool value
)
115 void sim_t::set_log(bool value
)
120 void sim_t::set_histogram(bool value
)
122 histogram_enabled
= value
;
123 for (size_t i
= 0; i
< procs
.size(); i
++) {
124 procs
[i
]->set_histogram(histogram_enabled
);
128 void sim_t::set_procs_debug(bool value
)
130 for (size_t i
=0; i
< procs
.size(); i
++)
131 procs
[i
]->set_debug(value
);
134 bool sim_t::mmio_load(reg_t addr
, size_t len
, uint8_t* bytes
)
136 if (addr
+ len
< addr
)
138 return bus
.load(addr
, len
, bytes
);
141 bool sim_t::mmio_store(reg_t addr
, size_t len
, const uint8_t* bytes
)
143 if (addr
+ len
< addr
)
145 return bus
.store(addr
, len
, bytes
);
148 static std::string
dts_compile(const std::string
& dts
)
150 // Convert the DTS to DTB
154 if (pipe(dts_pipe
) != 0 || (dts_pid
= fork()) < 0) {
155 std::cerr
<< "Failed to fork dts child: " << strerror(errno
) << std::endl
;
159 // Child process to output dts
162 int step
, len
= dts
.length();
163 const char *buf
= dts
.c_str();
164 for (int done
= 0; done
< len
; done
+= step
) {
165 step
= write(dts_pipe
[1], buf
+done
, len
-done
);
167 std::cerr
<< "Failed to write dts: " << strerror(errno
) << std::endl
;
177 if (pipe(dtb_pipe
) != 0 || (dtb_pid
= fork()) < 0) {
178 std::cerr
<< "Failed to fork dtb child: " << strerror(errno
) << std::endl
;
182 // Child process to output dtb
184 dup2(dts_pipe
[0], 0);
185 dup2(dtb_pipe
[1], 1);
190 execl(DTC
, DTC
, "-O", "dtb", 0);
191 std::cerr
<< "Failed to run " DTC
": " << strerror(errno
) << std::endl
;
200 std::stringstream dtb
;
204 while ((got
= read(dtb_pipe
[0], buf
, sizeof(buf
))) > 0) {
208 std::cerr
<< "Failed to read dtb: " << strerror(errno
) << std::endl
;
215 waitpid(dts_pid
, &status
, 0);
216 if (!WIFEXITED(status
) || WEXITSTATUS(status
) != 0) {
217 std::cerr
<< "Child dts process failed" << std::endl
;
220 waitpid(dtb_pid
, &status
, 0);
221 if (!WIFEXITED(status
) || WEXITSTATUS(status
) != 0) {
222 std::cerr
<< "Child dtb process failed" << std::endl
;
229 void sim_t::make_dtb()
231 const int reset_vec_size
= 8;
233 reg_t pc_delta
= start_pc
- DEFAULT_RSTVEC
;
234 reg_t pc_delta_hi
= (pc_delta
+ 0x800U
) & ~reg_t(0xfffU
);
235 reg_t pc_delta_lo
= pc_delta
- pc_delta_hi
;
236 if ((pc_delta_hi
>> 31) != 0 && (pc_delta_hi
>> 31) != reg_t(-1) >> 31) {
237 fprintf(stderr
, "initial pc %" PRIx64
" out of range\n", pc_delta
);
241 uint32_t reset_vec
[reset_vec_size
] = {
242 0x297 + uint32_t(pc_delta_hi
), // auipc t0, &pc
243 0x597, // auipc a1, &dtb
244 0x58593 + ((reset_vec_size
- 1) * 4 << 20), // addi a1, a1, &dtb
245 0xf1402573, // csrr a0, mhartid
246 0x28067 + uint32_t(pc_delta_lo
<< 20) // jalr zero, t0, &pc
249 std::vector
<char> rom((char*)reset_vec
, (char*)reset_vec
+ sizeof(reset_vec
));
256 " #address-cells = <2>;\n"
257 " #size-cells = <2>;\n"
258 " compatible = \"ucbbar,spike-bare-dev\";\n"
259 " model = \"ucbbar,spike-bare\";\n"
261 " #address-cells = <1>;\n"
262 " #size-cells = <0>;\n"
263 " timebase-frequency = <" << (CPU_HZ
/INSNS_PER_RTC_TICK
) << ">;\n";
264 for (size_t i
= 0; i
< procs
.size(); i
++) {
265 s
<< " CPU" << i
<< ": cpu@" << i
<< " {\n"
266 " device_type = \"cpu\";\n"
267 " reg = <" << i
<< ">;\n"
268 " status = \"okay\";\n"
269 " compatible = \"riscv\";\n"
270 " riscv,isa = \"" << procs
[i
]->isa_string
<< "\";\n"
271 " mmu-type = \"riscv," << (procs
[i
]->max_xlen
<= 32 ? "sv32" : "sv48") << "\";\n"
272 " clock-frequency = <" << CPU_HZ
<< ">;\n"
273 " CPU" << i
<< "_intc: interrupt-controller {\n"
274 " #interrupt-cells = <1>;\n"
275 " interrupt-controller;\n"
276 " compatible = \"riscv,cpu-intc\";\n"
281 for (auto& m
: mems
) {
283 " memory@" << m
.first
<< " {\n"
284 " device_type = \"memory\";\n"
285 " reg = <0x" << (m
.first
>> 32) << " 0x" << (m
.first
& (uint32_t)-1) <<
286 " 0x" << (m
.second
->size() >> 32) << " 0x" << (m
.second
->size() & (uint32_t)-1) << ">;\n"
290 " #address-cells = <2>;\n"
291 " #size-cells = <2>;\n"
292 " compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n"
294 " clint@" << CLINT_BASE
<< " {\n"
295 " compatible = \"riscv,clint0\";\n"
296 " interrupts-extended = <" << std::dec
;
297 for (size_t i
= 0; i
< procs
.size(); i
++)
298 s
<< "&CPU" << i
<< "_intc 3 &CPU" << i
<< "_intc 7 ";
299 reg_t clintbs
= CLINT_BASE
;
300 reg_t clintsz
= CLINT_SIZE
;
301 s
<< std::hex
<< ">;\n"
302 " reg = <0x" << (clintbs
>> 32) << " 0x" << (clintbs
& (uint32_t)-1) <<
303 " 0x" << (clintsz
>> 32) << " 0x" << (clintsz
& (uint32_t)-1) << ">;\n"
309 std::string dtb
= dts_compile(dts
);
311 rom
.insert(rom
.end(), dtb
.begin(), dtb
.end());
312 const int align
= 0x1000;
313 rom
.resize((rom
.size() + align
- 1) / align
* align
);
315 boot_rom
.reset(new rom_device_t(rom
));
316 bus
.add_device(DEFAULT_RSTVEC
, boot_rom
.get());
319 char* sim_t::addr_to_mem(reg_t addr
) {
320 auto desc
= bus
.find_device(addr
);
321 if (auto mem
= dynamic_cast<mem_t
*>(desc
.device
))
322 return mem
->contents() + (addr
- desc
.base
);
333 void sim_t::read_chunk(addr_t taddr
, size_t len
, void* dst
)
336 auto data
= debug_mmu
->load_uint64(taddr
);
337 memcpy(dst
, &data
, sizeof data
);
340 void sim_t::write_chunk(addr_t taddr
, size_t len
, const void* src
)
344 memcpy(&data
, src
, sizeof data
);
345 debug_mmu
->store_uint64(taddr
, data
);