riscv/sim.cc

   1 // See LICENSE for license details.
   2
   3 #include "sim.h"
   4 #include "mmu.h"
   5 #include "gdbserver.h"
   6 #include <map>
   7 #include <iostream>
   8 #include <sstream>
   9 #include <climits>
  10 #include <cstdlib>
  11 #include <cassert>
  12 #include <signal.h>
  13 #include <unistd.h>
  14 #include <sys/wait.h>
  15 #include <sys/types.h>
  16
  17 volatile bool ctrlc_pressed = false;
  18 static void handle_signal(int sig)
  19 {
  20   if (ctrlc_pressed)
  21     exit(-1);
  22   ctrlc_pressed = true;
  23   signal(sig, &handle_signal);
  24 }
  25
  26 sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted,
  27              const std::vector<std::string>& args)
  28   : htif_t(args), procs(std::max(nprocs, size_t(1))),
  29     current_step(0), current_proc(0), debug(false), gdbserver(NULL)
  30 {
  31   signal(SIGINT, &handle_signal);
  32   // allocate target machine's memory, shrinking it as necessary
  33   // until the allocation succeeds
  34   size_t memsz0 = (size_t)mem_mb << 20;
  35   size_t quantum = 1L << 20;
  36   if (memsz0 == 0)
  37     memsz0 = (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20;
  38
  39   memsz = memsz0;
  40   while ((mem = (char*)calloc(1, memsz)) == NULL)
  41     memsz = (size_t)(memsz*0.9)/quantum*quantum;
  42
  43   if (memsz != memsz0)
  44     fprintf(stderr, "warning: only got %zu bytes of target mem (wanted %zu)\n",
  45             memsz, memsz0);
  46
  47   bus.add_device(DEBUG_START, &debug_module);
  48
  49   debug_mmu = new mmu_t(this, NULL);
  50
  51   for (size_t i = 0; i < procs.size(); i++) {
  52     procs[i] = new processor_t(isa, this, i, halted);
  53   }
  54
  55   rtc.reset(new rtc_t(procs));
  56   make_dtb();
  57 }
  58
  59 sim_t::~sim_t()
  60 {
  61   for (size_t i = 0; i < procs.size(); i++)
  62     delete procs[i];
  63   delete debug_mmu;
  64   free(mem);
  65 }
  66
  67 void sim_thread_main(void* arg)
  68 {
  69   ((sim_t*)arg)->main();
  70 }
  71
  72 void sim_t::main()
  73 {
  74   if (!debug && log)
  75     set_procs_debug(true);
  76
  77   while (!done())
  78   {
  79     if (debug || ctrlc_pressed)
  80       interactive();
  81     else
  82       step(INTERLEAVE);
  83     if (gdbserver) {
  84       gdbserver->handle();
  85     }
  86   }
  87 }
  88
  89 int sim_t::run()
  90 {
  91   host = context_t::current();
  92   target.init(sim_thread_main, this);
  93   return htif_t::run();
  94 }
  95
  96 void sim_t::step(size_t n)
  97 {
  98   for (size_t i = 0, steps = 0; i < n; i += steps)
  99   {
 100     steps = std::min(n - i, INTERLEAVE - current_step);
 101     procs[current_proc]->step(steps);
 102
 103     current_step += steps;
 104     if (current_step == INTERLEAVE)
 105     {
 106       current_step = 0;
 107       procs[current_proc]->yield_load_reservation();
 108       if (++current_proc == procs.size()) {
 109         current_proc = 0;
 110         rtc->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
 111       }
 112
 113       host->switch_to();
 114     }
 115   }
 116 }
 117
 118 void sim_t::set_debug(bool value)
 119 {
 120   debug = value;
 121 }
 122
 123 void sim_t::set_log(bool value)
 124 {
 125   log = value;
 126 }
 127
 128 void sim_t::set_histogram(bool value)
 129 {
 130   histogram_enabled = value;
 131   for (size_t i = 0; i < procs.size(); i++) {
 132     procs[i]->set_histogram(histogram_enabled);
 133   }
 134 }
 135
 136 void sim_t::set_procs_debug(bool value)
 137 {
 138   for (size_t i=0; i< procs.size(); i++)
 139     procs[i]->set_debug(value);
 140 }
 141
 142 bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes)
 143 {
 144   if (addr + len < addr)
 145     return false;
 146   return bus.load(addr, len, bytes);
 147 }
 148
 149 bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
 150 {
 151   if (addr + len < addr)
 152     return false;
 153   return bus.store(addr, len, bytes);
 154 }
 155
 156 static std::string dts_compile(const std::string& dts)
 157 {
 158   // Convert the DTS to DTB
 159   int dts_pipe[2];
 160   pid_t dts_pid;
 161
 162   if (pipe(dts_pipe) != 0 || (dts_pid = fork()) < 0) {
 163     std::cerr << "Failed to fork dts child: " << strerror(errno) << std::endl;
 164     exit(1);
 165   }
 166
 167   // Child process to output dts
 168   if (dts_pid == 0) {
 169     close(dts_pipe[0]);
 170     int step, len = dts.length();
 171     const char *buf = dts.c_str();
 172     for (int done = 0; done < len; done += step) {
 173       step = write(dts_pipe[1], buf+done, len-done);
 174       if (step == -1) {
 175         std::cerr << "Failed to write dts: " << strerror(errno) << std::endl;
 176         exit(1);
 177       }
 178     }
 179     close(dts_pipe[1]);
 180     exit(0);
 181   }
 182
 183   pid_t dtb_pid;
 184   int dtb_pipe[2];
 185   if (pipe(dtb_pipe) != 0 || (dtb_pid = fork()) < 0) {
 186     std::cerr << "Failed to fork dtb child: " << strerror(errno) << std::endl;
 187     exit(1);
 188   }
 189
 190   // Child process to output dtb
 191   if (dtb_pid == 0) {
 192     dup2(dts_pipe[0], 0);
 193     dup2(dtb_pipe[1], 1);
 194     close(dts_pipe[0]);
 195     close(dts_pipe[1]);
 196     close(dtb_pipe[0]);
 197     close(dtb_pipe[1]);
 198     execl(DTC, DTC, "-O", "dtb", 0);
 199     std::cerr << "Failed to run " DTC ": " << strerror(errno) << std::endl;
 200     exit(1);
 201   }
 202
 203   close(dts_pipe[1]);
 204   close(dts_pipe[0]);
 205   close(dtb_pipe[1]);
 206
 207   // Read-out dtb
 208   std::stringstream dtb;
 209
 210   int got;
 211   char buf[4096];
 212   while ((got = read(dtb_pipe[0], buf, sizeof(buf))) > 0) {
 213     dtb.write(buf, got);
 214   }
 215   if (got == -1) {
 216     std::cerr << "Failed to read dtb: " << strerror(errno) << std::endl;
 217     exit(1);
 218   }
 219   close(dtb_pipe[0]);
 220
 221   // Reap children
 222   int status;
 223   waitpid(dts_pid, &status, 0);
 224   if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) {
 225     std::cerr << "Child dts process failed" << std::endl;
 226     exit(1);
 227   }
 228   waitpid(dtb_pid, &status, 0);
 229   if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) {
 230     std::cerr << "Child dtb process failed" << std::endl;
 231     exit(1);
 232   }
 233
 234   return dtb.str();
 235 }
 236
 237 void sim_t::make_dtb()
 238 {
 239   reg_t rtc_addr = EXT_IO_BASE;
 240   bus.add_device(rtc_addr, rtc.get());
 241
 242   const int align = 0x1000;
 243   reg_t cpu_addr = rtc_addr + ((rtc->size() - 1) / align + 1) * align;
 244   reg_t cpu_size = align;
 245
 246   uint32_t reset_vec[] = {
 247     0x297 + DRAM_BASE - DEFAULT_RSTVEC, // auipc t0, DRAM_BASE
 248     0x597,                              // auipc a1, 0
 249     0x58593,                            // addi a1, a1, 0
 250     0xf1402573,                         // csrr a0,mhartid
 251     0x00028067                          // jalr zero, t0, 0 (jump straight to DRAM_BASE)
 252   };
 253   reset_vec[2] += (sizeof(reset_vec) - 4) << 20; // addi a1, a1, sizeof(reset_vec) - 4 = DTB start
 254
 255   std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
 256
 257   std::stringstream s;
 258   s << std::dec <<
 259          "/dts-v1/;\n"
 260          "\n"
 261          "/ {\n"
 262          "  #address-cells = <2>;\n"
 263          "  #size-cells = <2>;\n"
 264          "  compatible = \"ucbbar,spike-bare-dev\";\n"
 265          "  model = \"ucbbar,spike-bare\";\n"
 266          "  cpus {\n"
 267          "    #address-cells = <1>;\n"
 268          "    #size-cells = <0>;\n"
 269          "    timebase-frequency = <" << (CPU_HZ/INSNS_PER_RTC_TICK) << ">;\n";
 270   for (size_t i = 0; i < procs.size(); i++) {
 271     s << "    CPU" << i << ": cpu@" << i << " {\n"
 272          "      device_type = \"cpu\";\n"
 273          "      reg = <" << i << ">;\n"
 274          "      status = \"okay\";\n"
 275          "      compatible = \"riscv\";\n"
 276          "      riscv,isa = \"" << procs[i]->isa_string << "\";\n"
 277          "      mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n"
 278          "      clock-frequency = <" << CPU_HZ << ">;\n"
 279          "    };\n";
 280   }
 281   reg_t membs = DRAM_BASE;
 282   s << std::hex <<
 283          "  };\n"
 284          "  memory@" << DRAM_BASE << " {\n"
 285          "    device_type = \"memory\";\n"
 286          "    reg = <0x" << (membs >> 32) << " 0x" << (membs & (uint32_t)-1) <<
 287                    " 0x" << (memsz >> 32) << " 0x" << (memsz & (uint32_t)-1) << ">;\n"
 288          "  };\n"
 289          "  soc {\n"
 290          "    #address-cells = <2>;\n"
 291          "    #size-cells = <2>;\n"
 292          "    compatible = \"ucbbar,spike-bare-soc\";\n"
 293          "    ranges;\n"
 294          "    clint@" << rtc_addr << " {\n"
 295          "      compatible = \"riscv,clint0\";\n"
 296          "      interrupts-extended = <" << std::dec;
 297   for (size_t i = 0; i < procs.size(); i++)
 298     s << "&CPU" << i << " 3 &CPU" << i << " 7 ";
 299   s << std::hex << ">;\n"
 300          "      reg = <0x" << (rtc_addr >> 32) << " 0x" << (rtc_addr & (uint32_t)-1) <<
 301                      " 0x0 0x10000>;\n"
 302          "    };\n"
 303          "  };\n"
 304          "};\n";
 305
 306   dts = s.str();
 307   std::string dtb = dts_compile(dts);
 308
 309   rom.insert(rom.end(), dtb.begin(), dtb.end());
 310   rom.resize((rom.size() / align + 1) * align);
 311
 312   boot_rom.reset(new rom_device_t(rom));
 313   bus.add_device(DEFAULT_RSTVEC, boot_rom.get());
 314 }
 315
 316 // htif
 317
 318 void sim_t::idle()
 319 {
 320   target.switch_to();
 321 }
 322
 323 void sim_t::read_chunk(addr_t taddr, size_t len, void* dst)
 324 {
 325   assert(len == 8);
 326   auto data = debug_mmu->load_uint64(taddr);
 327   memcpy(dst, &data, sizeof data);
 328 }
 329
 330 void sim_t::write_chunk(addr_t taddr, size_t len, const void* src)
 331 {
 332   assert(len == 8);
 333   uint64_t data;
 334   memcpy(&data, src, sizeof data);
 335   debug_mmu->store_uint64(taddr, data);
 336 }