riscv/sim.cc

   1 // See LICENSE for license details.
   2
   3 #include "sim.h"
   4 #include "mmu.h"
   5 #include "htif.h"
   6 #include "gdbserver.h"
   7 #include <map>
   8 #include <iostream>
   9 #include <sstream>
  10 #include <climits>
  11 #include <cstdlib>
  12 #include <cassert>
  13 #include <signal.h>
  14
  15 volatile bool ctrlc_pressed = false;
  16 static void handle_signal(int sig)
  17 {
  18   if (ctrlc_pressed)
  19     exit(-1);
  20   ctrlc_pressed = true;
  21   signal(sig, &handle_signal);
  22 }
  23
  24 sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted,
  25              const std::vector<std::string>& args)
  26   : htif(new htif_isasim_t(this, args)), procs(std::max(nprocs, size_t(1))),
  27     current_step(0), current_proc(0), debug(false), gdbserver(NULL)
  28 {
  29   signal(SIGINT, &handle_signal);
  30   // allocate target machine's memory, shrinking it as necessary
  31   // until the allocation succeeds
  32   size_t memsz0 = (size_t)mem_mb << 20;
  33   size_t quantum = 1L << 20;
  34   if (memsz0 == 0)
  35     memsz0 = (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20;
  36
  37   memsz = memsz0;
  38   while ((mem = (char*)calloc(1, memsz)) == NULL)
  39     memsz = (size_t)(memsz*0.9)/quantum*quantum;
  40
  41   if (memsz != memsz0)
  42     fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n",
  43             (unsigned long)memsz, (unsigned long)memsz0);
  44
  45   bus.add_device(DEBUG_START, &debug_module);
  46
  47   debug_mmu = new mmu_t(this, NULL);
  48
  49   for (size_t i = 0; i < procs.size(); i++) {
  50     procs[i] = new processor_t(isa, this, i, halted);
  51   }
  52
  53   rtc.reset(new rtc_t(procs));
  54   make_config_string();
  55 }
  56
  57 sim_t::~sim_t()
  58 {
  59   for (size_t i = 0; i < procs.size(); i++)
  60     delete procs[i];
  61   delete debug_mmu;
  62   free(mem);
  63 }
  64
  65 int sim_t::run()
  66 {
  67   if (!debug && log)
  68     set_procs_debug(true);
  69   while (htif->tick())
  70   {
  71     if (debug || ctrlc_pressed)
  72       interactive();
  73     else
  74       step(INTERLEAVE);
  75     if (gdbserver) {
  76         gdbserver->handle();
  77     }
  78   }
  79   return htif->exit_code();
  80 }
  81
  82 void sim_t::step(size_t n)
  83 {
  84   for (size_t i = 0, steps = 0; i < n; i += steps)
  85   {
  86     steps = std::min(n - i, INTERLEAVE - current_step);
  87     procs[current_proc]->step(steps);
  88
  89     current_step += steps;
  90     if (current_step == INTERLEAVE)
  91     {
  92       current_step = 0;
  93       procs[current_proc]->yield_load_reservation();
  94       if (++current_proc == procs.size()) {
  95         current_proc = 0;
  96         rtc->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
  97       }
  98
  99       htif->tick();
 100     }
 101   }
 102 }
 103
 104 bool sim_t::running()
 105 {
 106   for (size_t i = 0; i < procs.size(); i++)
 107     if (procs[i]->running())
 108       return true;
 109   return false;
 110 }
 111
 112 void sim_t::set_debug(bool value)
 113 {
 114   debug = value;
 115 }
 116
 117 void sim_t::set_log(bool value)
 118 {
 119   log = value;
 120 }
 121
 122 void sim_t::set_histogram(bool value)
 123 {
 124   histogram_enabled = value;
 125   for (size_t i = 0; i < procs.size(); i++) {
 126     procs[i]->set_histogram(histogram_enabled);
 127   }
 128 }
 129
 130 void sim_t::set_procs_debug(bool value)
 131 {
 132   for (size_t i=0; i< procs.size(); i++)
 133     procs[i]->set_debug(value);
 134 }
 135
 136 bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes)
 137 {
 138   if (addr + len < addr)
 139     return false;
 140   return bus.load(addr, len, bytes);
 141 }
 142
 143 bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
 144 {
 145   if (addr + len < addr)
 146     return false;
 147   return bus.store(addr, len, bytes);
 148 }
 149
 150 void sim_t::make_config_string()
 151 {
 152   reg_t rtc_addr = EXT_IO_BASE;
 153   bus.add_device(rtc_addr, rtc.get());
 154
 155   const int align = 0x1000;
 156   reg_t cpu_addr = rtc_addr + ((rtc->size() - 1) / align + 1) * align;
 157   reg_t cpu_size = align;
 158
 159   uint32_t reset_vec[8] = {
 160     0x297 + DRAM_BASE - DEFAULT_RSTVEC, // reset vector
 161     0x00028067,                         //   jump straight to DRAM_BASE
 162     0x00000000,                         // reserved
 163     0,                                  // config string pointer
 164     0, 0, 0, 0                          // trap vector
 165   };
 166   reset_vec[3] = DEFAULT_RSTVEC + sizeof(reset_vec); // config string pointer
 167
 168   std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
 169
 170   std::stringstream s;
 171   s << std::hex <<
 172         "platform {\n"
 173         "  vendor ucb;\n"
 174         "  arch spike;\n"
 175         "};\n"
 176         "rtc {\n"
 177         "  addr 0x" << rtc_addr << ";\n"
 178         "};\n"
 179         "ram {\n"
 180         "  0 {\n"
 181         "    addr 0x" << DRAM_BASE << ";\n"
 182         "    size 0x" << memsz << ";\n"
 183         "  };\n"
 184         "};\n"
 185         "core {\n";
 186   for (size_t i = 0; i < procs.size(); i++) {
 187     s <<
 188         "  " << i << " {\n"
 189         "    " << "0 {\n" << // hart 0 on core i
 190         "      isa " << procs[i]->isa_string << ";\n"
 191         "      timecmp 0x" << (rtc_addr + 8*(1+i)) << ";\n"
 192         "      ipi 0x" << cpu_addr << ";\n"
 193         "    };\n"
 194         "  };\n";
 195     bus.add_device(cpu_addr, procs[i]);
 196     cpu_addr += cpu_size;
 197   }
 198   s <<  "};\n";
 199
 200   config_string = s.str();
 201   rom.insert(rom.end(), config_string.begin(), config_string.end());
 202   rom.resize((rom.size() / align + 1) * align);
 203
 204   boot_rom.reset(new rom_device_t(rom));
 205   bus.add_device(DEFAULT_RSTVEC, boot_rom.get());
 206 }