riscv/sim.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_SIM_H
   4 #define _RISCV_SIM_H
   5
   6 #include <vector>
   7 #include <string>
   8 #include <memory>
   9 #include "processor.h"
  10 #include "mmu.h"
  11
  12 class htif_isasim_t;
  13
  14 // this class encapsulates the processors and memory in a RISC-V machine.
  15 class sim_t
  16 {
  17 public:
  18   sim_t(size_t _nprocs, size_t mem_mb, const std::vector<std::string>& htif_args);
  19   ~sim_t();
  20
  21   // run the simulation to completion
  22   int run();
  23   bool running();
  24   void stop();
  25   void set_debug(bool value);
  26   void set_histogram(bool value);
  27   void set_procs_debug(bool value);
  28   htif_isasim_t* get_htif() { return htif.get(); }
  29
  30   // deliver an IPI to a specific processor
  31   void send_ipi(reg_t who);
  32
  33   // returns the number of processors in this simulator
  34   size_t num_cores() { return procs.size(); }
  35   processor_t* get_core(size_t i) { return procs.at(i); }
  36
  37   // read one of the system control registers
  38   reg_t get_scr(int which);
  39
  40 private:
  41   std::unique_ptr<htif_isasim_t> htif;
  42   char* mem; // main memory
  43   size_t memsz; // memory size in bytes
  44   mmu_t* debug_mmu;  // debug port into main memory
  45   std::vector<processor_t*> procs;
  46
  47   void step(size_t n); // step through simulation
  48   static const size_t INTERLEAVE = 5000;
  49   size_t current_step;
  50   size_t current_proc;
  51   bool debug;
  52   bool histogram_enabled; // provide a histogram of PCs
  53
  54   // presents a prompt for introspection into the simulation
  55   void interactive();
  56
  57   // functions that help implement interactive()
  58   void interactive_quit(const std::string& cmd, const std::vector<std::string>& args);
  59   void interactive_run(const std::string& cmd, const std::vector<std::string>& args, bool noisy);
  60   void interactive_run_noisy(const std::string& cmd, const std::vector<std::string>& args);
  61   void interactive_run_silent(const std::string& cmd, const std::vector<std::string>& args);
  62   void interactive_reg(const std::string& cmd, const std::vector<std::string>& args);
  63   void interactive_fregs(const std::string& cmd, const std::vector<std::string>& args);
  64   void interactive_fregd(const std::string& cmd, const std::vector<std::string>& args);
  65   void interactive_mem(const std::string& cmd, const std::vector<std::string>& args);
  66   void interactive_str(const std::string& cmd, const std::vector<std::string>& args);
  67   void interactive_until(const std::string& cmd, const std::vector<std::string>& args);
  68   reg_t get_reg(const std::vector<std::string>& args);
  69   reg_t get_freg(const std::vector<std::string>& args);
  70   reg_t get_mem(const std::vector<std::string>& args);
  71   reg_t get_pc(const std::vector<std::string>& args);
  72   reg_t get_tohost(const std::vector<std::string>& args);
  73
  74   friend class htif_isasim_t;
  75 };
  76
  77 extern volatile bool ctrlc_pressed;
  78
  79 #endif