d09da3f703ad1b0566726ecf899694b07be12f75
[riscv-isa-sim.git] / riscv / trap.h
1 #ifndef _RISCV_TRAP_H
2 #define _RISCV_TRAP_H
3
4 #define TRAP_LIST \
5 DECLARE_TRAP(instruction_address_misaligned), \
6 DECLARE_TRAP(instruction_access_fault), \
7 DECLARE_TRAP(illegal_instruction), \
8 DECLARE_TRAP(privileged_instruction), \
9 DECLARE_TRAP(fp_disabled), \
10 DECLARE_TRAP(reserved0), \
11 DECLARE_TRAP(syscall), \
12 DECLARE_TRAP(breakpoint), \
13 DECLARE_TRAP(load_address_misaligned), \
14 DECLARE_TRAP(store_address_misaligned), \
15 DECLARE_TRAP(load_access_fault), \
16 DECLARE_TRAP(store_access_fault), \
17 DECLARE_TRAP(vector_disabled), \
18 DECLARE_TRAP(vector_bank), \
19 DECLARE_TRAP(vector_illegal_instruction), \
20 DECLARE_TRAP(reserved1), \
21
22 #define DECLARE_TRAP(x) trap_##x
23 enum trap_t
24 {
25 TRAP_LIST
26 NUM_TRAPS
27 };
28 #undef DECLARE_TRAP
29
30 struct interrupt_t { interrupt_t(int which) : i(which) {} int i; };
31 struct halt_t {}; // thrown to stop the processor from running
32
33 extern "C" const char* trap_name(trap_t t);
34
35 #endif