275fb561ccf518b91711b445a1e9f505e334f1f8
1 // See LICENSE for license details.
11 struct : public arg_t
{
12 std::string
to_string(insn_t insn
) const {
13 return std::to_string((int)insn
.i_imm()) + '(' + xpr_name
[insn
.rs1()] + ')';
17 struct : public arg_t
{
18 std::string
to_string(insn_t insn
) const {
19 return std::to_string((int)insn
.s_imm()) + '(' + xpr_name
[insn
.rs1()] + ')';
23 struct : public arg_t
{
24 std::string
to_string(insn_t insn
) const {
25 return std::string("0(") + xpr_name
[insn
.rs1()] + ')';
29 struct : public arg_t
{
30 std::string
to_string(insn_t insn
) const {
31 return xpr_name
[insn
.rd()];
35 struct : public arg_t
{
36 std::string
to_string(insn_t insn
) const {
37 return xpr_name
[insn
.rs1()];
41 struct : public arg_t
{
42 std::string
to_string(insn_t insn
) const {
43 return xpr_name
[insn
.rs2()];
47 struct : public arg_t
{
48 std::string
to_string(insn_t insn
) const {
49 return fpr_name
[insn
.rd()];
53 struct : public arg_t
{
54 std::string
to_string(insn_t insn
) const {
55 return fpr_name
[insn
.rs1()];
59 struct : public arg_t
{
60 std::string
to_string(insn_t insn
) const {
61 return fpr_name
[insn
.rs2()];
65 struct : public arg_t
{
66 std::string
to_string(insn_t insn
) const {
67 return fpr_name
[insn
.rs3()];
71 struct : public arg_t
{
72 std::string
to_string(insn_t insn
) const {
75 #define DECLARE_CSR(name, num) case num: return #name;
78 default: return "unknown";
83 struct : public arg_t
{
84 std::string
to_string(insn_t insn
) const {
85 return std::to_string((int)insn
.i_imm());
89 struct : public arg_t
{
90 std::string
to_string(insn_t insn
) const {
92 s
<< std::hex
<< "0x" << ((uint32_t)insn
.u_imm() >> 12);
97 struct : public arg_t
{
98 std::string
to_string(insn_t insn
) const {
99 return std::to_string(insn
.rs1());
103 struct : public arg_t
{
104 std::string
to_string(insn_t insn
) const {
106 int32_t target
= insn
.sb_imm();
107 char sign
= target
>= 0 ? '+' : '-';
108 s
<< "pc " << sign
<< ' ' << abs(target
);
113 struct : public arg_t
{
114 std::string
to_string(insn_t insn
) const {
116 int32_t target
= insn
.uj_imm();
117 char sign
= target
>= 0 ? '+' : '-';
118 s
<< "pc " << sign
<< std::hex
<< " 0x" << abs(target
);
123 struct : public arg_t
{
124 std::string
to_string(insn_t insn
) const {
125 return xpr_name
[insn
.rvc_rs1()];
129 struct : public arg_t
{
130 std::string
to_string(insn_t insn
) const {
131 return xpr_name
[insn
.rvc_rds()];
135 struct : public arg_t
{
136 std::string
to_string(insn_t insn
) const {
137 return xpr_name
[insn
.rvc_rs1s()];
141 struct : public arg_t
{
142 std::string
to_string(insn_t insn
) const {
143 return std::to_string((int)insn
.rvc_imm());
147 struct : public arg_t
{
148 std::string
to_string(insn_t insn
) const {
149 return std::to_string((int)insn
.rvc_lwsp_imm());
153 struct : public arg_t
{
154 std::string
to_string(insn_t insn
) const {
155 return std::to_string((int)(insn
.rvc_imm() & 0x3f));
159 struct : public arg_t
{
160 std::string
to_string(insn_t insn
) const {
162 s
<< std::hex
<< "0x" << (uint32_t)insn
.rvc_imm();
167 struct : public arg_t
{
168 std::string
to_string(insn_t insn
) const {
169 return std::to_string((int)insn
.rvc_lwsp_imm()) + '(' + xpr_name
[2] + ')';
173 struct : public arg_t
{
174 std::string
to_string(insn_t insn
) const {
175 return std::to_string((int)insn
.rvc_ldsp_imm()) + '(' + xpr_name
[2] + ')';
179 struct : public arg_t
{
180 std::string
to_string(insn_t insn
) const {
181 return std::to_string((int)insn
.rvc_lw_imm()) + '(' + xpr_name
[insn
.rvc_rs1s()] + ')';
185 struct : public arg_t
{
186 std::string
to_string(insn_t insn
) const {
187 return std::to_string((int)insn
.rvc_ld_imm()) + '(' + xpr_name
[insn
.rvc_rs1s()] + ')';
191 struct : public arg_t
{
192 std::string
to_string(insn_t insn
) const {
194 int32_t target
= insn
.rvc_b_imm();
195 char sign
= target
>= 0 ? '+' : '-';
196 s
<< "pc " << sign
<< ' ' << abs(target
);
201 struct : public arg_t
{
202 std::string
to_string(insn_t insn
) const {
204 int32_t target
= insn
.rvc_j_imm();
205 char sign
= target
>= 0 ? '+' : '-';
206 s
<< "pc " << sign
<< ' ' << abs(target
);
211 std::string
disassembler_t::disassemble(insn_t insn
)
213 const disasm_insn_t
* disasm_insn
= lookup(insn
);
214 return disasm_insn
? disasm_insn
->to_string(insn
) : "unknown";
217 disassembler_t::disassembler_t()
219 const uint32_t mask_rd
= 0x1fUL
<< 7;
220 const uint32_t match_rd_ra
= 1UL << 7;
221 const uint32_t mask_rs1
= 0x1fUL
<< 15;
222 const uint32_t match_rs1_ra
= 1UL << 15;
223 const uint32_t mask_rvc_rs1
= 0x1fUL
<< 2;
224 const uint32_t match_rvc_rs1_ra
= 1UL << 2;
225 const uint32_t mask_rs2
= 0x1fUL
<< 20;
226 const uint32_t mask_imm
= 0xfffUL
<< 20;
227 const uint32_t match_imm_1
= 1UL << 20;
229 #define DECLARE_INSN(code, match, mask) \
230 const uint32_t match_##code = match; \
231 const uint32_t mask_##code = mask;
232 #include "encoding.h"
235 // explicit per-instruction disassembly
236 #define DISASM_INSN(name, code, extra, ...) \
237 add_insn(new disasm_insn_t(name, match_##code, mask_##code | (extra), __VA_ARGS__));
238 #define DEFINE_NOARG(code) \
239 add_insn(new disasm_insn_t(#code, match_##code, mask_##code, {}));
240 #define DEFINE_RTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs1, &xrs2})
241 #define DEFINE_ITYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs1, &imm})
242 #define DEFINE_I0TYPE(name, code) DISASM_INSN(name, code, mask_rs1, {&xrd, &imm})
243 #define DEFINE_I1TYPE(name, code) DISASM_INSN(name, code, mask_imm, {&xrd, &xrs1})
244 #define DEFINE_I2TYPE(name, code) DISASM_INSN(name, code, mask_rd | mask_imm, {&xrs1})
245 #define DEFINE_LTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &bigimm})
246 #define DEFINE_BTYPE(code) DISASM_INSN(#code, code, 0, {&xrs1, &xrs2, &branch_target})
247 #define DEFINE_B0TYPE(name, code) DISASM_INSN(name, code, mask_rs1 | mask_rs2, {&branch_target})
248 #define DEFINE_B1TYPE(name, code) DISASM_INSN(name, code, mask_rs2, {&xrs1, &branch_target})
249 #define DEFINE_XLOAD(code) DISASM_INSN(#code, code, 0, {&xrd, &load_address})
250 #define DEFINE_XSTORE(code) DISASM_INSN(#code, code, 0, {&xrs2, &store_address})
251 #define DEFINE_XAMO(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs2, &amo_address})
252 #define DEFINE_FLOAD(code) DISASM_INSN(#code, code, 0, {&frd, &load_address})
253 #define DEFINE_FSTORE(code) DISASM_INSN(#code, code, 0, {&frs2, &store_address})
254 #define DEFINE_FRTYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1, &frs2})
255 #define DEFINE_FR1TYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1})
256 #define DEFINE_FR3TYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1, &frs2, &frs3})
257 #define DEFINE_FXTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &frs1})
258 #define DEFINE_XFTYPE(code) DISASM_INSN(#code, code, 0, {&frd, &xrs1})
273 DEFINE_XAMO(amoadd_w
)
274 DEFINE_XAMO(amoswap_w
)
275 DEFINE_XAMO(amoand_w
)
277 DEFINE_XAMO(amoxor_w
)
278 DEFINE_XAMO(amomin_w
)
279 DEFINE_XAMO(amomax_w
)
280 DEFINE_XAMO(amominu_w
)
281 DEFINE_XAMO(amomaxu_w
)
282 DEFINE_XAMO(amoadd_d
)
283 DEFINE_XAMO(amoswap_d
)
284 DEFINE_XAMO(amoand_d
)
286 DEFINE_XAMO(amoxor_d
)
287 DEFINE_XAMO(amomin_d
)
288 DEFINE_XAMO(amomax_d
)
289 DEFINE_XAMO(amominu_d
)
290 DEFINE_XAMO(amomaxu_d
)
303 add_insn(new disasm_insn_t("j", match_jal
, mask_jal
| mask_rd
, {&jump_target
}));
304 add_insn(new disasm_insn_t("jal", match_jal
| match_rd_ra
, mask_jal
| mask_rd
, {&jump_target
}));
305 add_insn(new disasm_insn_t("jal", match_jal
, mask_jal
, {&xrd
, &jump_target
}));
307 DEFINE_B1TYPE("beqz", beq
);
308 DEFINE_B1TYPE("bnez", bne
);
309 DEFINE_B1TYPE("bltz", blt
);
310 DEFINE_B1TYPE("bgez", bge
);
321 add_insn(new disasm_insn_t("ret", match_jalr
| match_rs1_ra
, mask_jalr
| mask_rd
| mask_rs1
| mask_imm
, {}));
322 DEFINE_I2TYPE("jr", jalr
);
323 add_insn(new disasm_insn_t("jalr", match_jalr
| match_rd_ra
, mask_jalr
| mask_rd
| mask_imm
, {&xrs1
}));
326 add_insn(new disasm_insn_t("nop", match_addi
, mask_addi
| mask_rd
| mask_rs1
| mask_imm
, {}));
327 add_insn(new disasm_insn_t(" - ", match_xor
, mask_xor
| mask_rd
| mask_rs1
| mask_rs2
, {})); // for machine-generated bubbles
328 DEFINE_I0TYPE("li", addi
);
329 DEFINE_I1TYPE("mv", addi
);
333 add_insn(new disasm_insn_t("seqz", match_sltiu
| match_imm_1
, mask_sltiu
| mask_imm
, {&xrd
, &xrs1
}));
335 add_insn(new disasm_insn_t("not", match_xori
| mask_imm
, mask_xori
| mask_imm
, {&xrd
, &xrs1
}));
341 DEFINE_I1TYPE("sext.w", addiw
);
351 add_insn(new disasm_insn_t("snez", match_sltu
, mask_sltu
| mask_rs1
, {&xrd
, &xrs2
}));
361 DEFINE_RTYPE(mulhsu
);
378 DEFINE_NOARG(sbreak
);
380 DEFINE_NOARG(fence_i
);
382 add_insn(new disasm_insn_t("csrr", match_csrrs
, mask_csrrs
| mask_rs1
, {&xrd
, &csr
}));
383 add_insn(new disasm_insn_t("csrw", match_csrrw
, mask_csrrw
| mask_rd
, {&csr
, &xrs1
}));
384 add_insn(new disasm_insn_t("csrs", match_csrrs
, mask_csrrs
| mask_rd
, {&csr
, &xrs1
}));
385 add_insn(new disasm_insn_t("csrc", match_csrrc
, mask_csrrc
| mask_rd
, {&csr
, &xrs1
}));
386 add_insn(new disasm_insn_t("csrwi", match_csrrwi
, mask_csrrwi
| mask_rd
, {&csr
, &zimm5
}));
387 add_insn(new disasm_insn_t("csrsi", match_csrrsi
, mask_csrrsi
| mask_rd
, {&csr
, &zimm5
}));
388 add_insn(new disasm_insn_t("csrci", match_csrrci
, mask_csrrci
| mask_rd
, {&csr
, &zimm5
}));
389 add_insn(new disasm_insn_t("csrrw", match_csrrw
, mask_csrrw
, {&xrd
, &csr
, &xrs1
}));
390 add_insn(new disasm_insn_t("csrrs", match_csrrs
, mask_csrrs
, {&xrd
, &csr
, &xrs1
}));
391 add_insn(new disasm_insn_t("csrrc", match_csrrc
, mask_csrrc
, {&xrd
, &csr
, &xrs1
}));
392 add_insn(new disasm_insn_t("csrrwi", match_csrrwi
, mask_csrrwi
, {&xrd
, &csr
, &zimm5
}));
393 add_insn(new disasm_insn_t("csrrsi", match_csrrsi
, mask_csrrsi
, {&xrd
, &csr
, &zimm5
}));
394 add_insn(new disasm_insn_t("csrrci", match_csrrci
, mask_csrrci
, {&xrd
, &csr
, &zimm5
}));
397 DEFINE_FRTYPE(fadd_s
);
398 DEFINE_FRTYPE(fsub_s
);
399 DEFINE_FRTYPE(fmul_s
);
400 DEFINE_FRTYPE(fdiv_s
);
401 DEFINE_FR1TYPE(fsqrt_s
);
402 DEFINE_FRTYPE(fmin_s
);
403 DEFINE_FRTYPE(fmax_s
);
404 DEFINE_FR3TYPE(fmadd_s
);
405 DEFINE_FR3TYPE(fmsub_s
);
406 DEFINE_FR3TYPE(fnmadd_s
);
407 DEFINE_FR3TYPE(fnmsub_s
);
408 DEFINE_FRTYPE(fsgnj_s
);
409 DEFINE_FRTYPE(fsgnjn_s
);
410 DEFINE_FRTYPE(fsgnjx_s
);
411 DEFINE_FR1TYPE(fcvt_s_d
);
412 DEFINE_XFTYPE(fcvt_s_l
);
413 DEFINE_XFTYPE(fcvt_s_lu
);
414 DEFINE_XFTYPE(fcvt_s_w
);
415 DEFINE_XFTYPE(fcvt_s_wu
);
416 DEFINE_XFTYPE(fcvt_s_wu
);
417 DEFINE_XFTYPE(fmv_s_x
);
418 DEFINE_FXTYPE(fcvt_l_s
);
419 DEFINE_FXTYPE(fcvt_lu_s
);
420 DEFINE_FXTYPE(fcvt_w_s
);
421 DEFINE_FXTYPE(fcvt_wu_s
);
422 DEFINE_FXTYPE(fclass_s
);
423 DEFINE_FXTYPE(fmv_x_s
);
424 DEFINE_FXTYPE(feq_s
);
425 DEFINE_FXTYPE(flt_s
);
426 DEFINE_FXTYPE(fle_s
);
428 DEFINE_FRTYPE(fadd_d
);
429 DEFINE_FRTYPE(fsub_d
);
430 DEFINE_FRTYPE(fmul_d
);
431 DEFINE_FRTYPE(fdiv_d
);
432 DEFINE_FR1TYPE(fsqrt_d
);
433 DEFINE_FRTYPE(fmin_d
);
434 DEFINE_FRTYPE(fmax_d
);
435 DEFINE_FR3TYPE(fmadd_d
);
436 DEFINE_FR3TYPE(fmsub_d
);
437 DEFINE_FR3TYPE(fnmadd_d
);
438 DEFINE_FR3TYPE(fnmsub_d
);
439 DEFINE_FRTYPE(fsgnj_d
);
440 DEFINE_FRTYPE(fsgnjn_d
);
441 DEFINE_FRTYPE(fsgnjx_d
);
442 DEFINE_FR1TYPE(fcvt_d_s
);
443 DEFINE_XFTYPE(fcvt_d_l
);
444 DEFINE_XFTYPE(fcvt_d_lu
);
445 DEFINE_XFTYPE(fcvt_d_w
);
446 DEFINE_XFTYPE(fcvt_d_wu
);
447 DEFINE_XFTYPE(fcvt_d_wu
);
448 DEFINE_XFTYPE(fmv_d_x
);
449 DEFINE_FXTYPE(fcvt_l_d
);
450 DEFINE_FXTYPE(fcvt_lu_d
);
451 DEFINE_FXTYPE(fcvt_w_d
);
452 DEFINE_FXTYPE(fcvt_wu_d
);
453 DEFINE_FXTYPE(fclass_d
);
454 DEFINE_FXTYPE(fmv_x_d
);
455 DEFINE_FXTYPE(feq_d
);
456 DEFINE_FXTYPE(flt_d
);
457 DEFINE_FXTYPE(fle_d
);
459 add_insn(new disasm_insn_t("sbreak", match_c_li
| 0x1000, 0xffff, {}));
460 DISASM_INSN("li", c_li
, 0, {&xrd
, &rvc_imm
});
461 DISASM_INSN("lui", c_lui
, 0, {&xrd
, &rvc_uimm
});
462 DISASM_INSN("addi", c_addi
, 0, {&xrd
, &xrd
, &rvc_imm
});
463 DISASM_INSN("addiw", c_addiw
, 0, {&xrd
, &xrd
, &rvc_imm
});
464 DISASM_INSN("slli", c_slli
, 0, {&xrd
, &rvc_shamt
});
465 DISASM_INSN("addi", c_addi4
, 0, {&xrd
, &xrd
, &rvc_lwsp_imm
});
466 DISASM_INSN("mv", c_mv
, 0, {&xrd
, &rvc_rs1
});
467 add_insn(new disasm_insn_t("ret", match_c_jalr
| match_rvc_rs1_ra
, mask_c_jalr
| mask_rd
| mask_rvc_rs1
, {}));
468 DISASM_INSN("jr", c_jalr
, mask_rd
, {&xrd
, &rvc_rs1
});
469 DISASM_INSN("jalr", c_jalr
, mask_rd
, {&xrd
, &rvc_rs1
});
470 DISASM_INSN("add", c_add
, 0, {&xrd
, &xrd
, &rvc_rs1
});
471 DISASM_INSN("addw", c_addw
, 0, {&xrd
, &xrd
, &rvc_rs1
});
472 DISASM_INSN("lw", c_lwsp
, 0, {&xrd
, &rvc_lwsp_address
});
473 DISASM_INSN("ld", c_ldsp
, 0, {&xrd
, &rvc_ldsp_address
});
474 DISASM_INSN("sw", c_swsp
, 0, {&xrd
, &rvc_lwsp_address
});
475 DISASM_INSN("sd", c_sdsp
, 0, {&xrd
, &rvc_ldsp_address
});
476 DISASM_INSN("lw", c_lw
, 0, {&rvc_rds
, &rvc_lw_address
});
477 DISASM_INSN("ld", c_ld
, 0, {&rvc_rds
, &rvc_ld_address
});
478 DISASM_INSN("sw", c_sw
, 0, {&rvc_rds
, &rvc_lw_address
});
479 DISASM_INSN("sd", c_sd
, 0, {&rvc_rds
, &rvc_ld_address
});
480 DISASM_INSN("beqz", c_beqz
, 0, {&rvc_rds
, &rvc_branch_target
});
481 DISASM_INSN("bnez", c_bnez
, 0, {&rvc_rds
, &rvc_branch_target
});
482 DISASM_INSN("j", c_j
, 0, {&rvc_jump_target
});
484 // provide a default disassembly for all instructions as a fallback
485 #define DECLARE_INSN(code, match, mask) \
486 add_insn(new disasm_insn_t(#code " (args unknown)", match, mask, {}));
487 #include "encoding.h"
491 const disasm_insn_t
* disassembler_t::lookup(insn_t insn
)
493 size_t idx
= insn
.bits() % HASH_SIZE
;
494 for (size_t j
= 0; j
< chain
[idx
].size(); j
++)
495 if(*chain
[idx
][j
] == insn
)
496 return chain
[idx
][j
];
499 for (size_t j
= 0; j
< chain
[idx
].size(); j
++)
500 if(*chain
[idx
][j
] == insn
)
501 return chain
[idx
][j
];
506 void disassembler_t::add_insn(disasm_insn_t
* insn
)
508 size_t idx
= HASH_SIZE
;
509 if (insn
->get_mask() % HASH_SIZE
== HASH_SIZE
- 1)
510 idx
= insn
->get_match() % HASH_SIZE
;
511 chain
[idx
].push_back(insn
);
514 disassembler_t::~disassembler_t()
516 for (size_t i
= 0; i
< HASH_SIZE
+1; i
++)
517 for (size_t j
= 0; j
< chain
[i
].size(); j
++)