spike_main/spike.cc

   1 // See LICENSE for license details.
   2
   3 #include "sim.h"
   4 #include "htif.h"
   5 #include "cachesim.h"
   6 #include "extension.h"
   7 #include <dlfcn.h>
   8 #include <fesvr/option_parser.h>
   9 #include <stdio.h>
  10 #include <stdlib.h>
  11 #include <getopt.h>
  12 #include <vector>
  13 #include <string>
  14 #include <memory>
  15
  16 static void help()
  17 {
  18   fprintf(stderr, "usage: spike [host options] <target program> [target options]\n");
  19   fprintf(stderr, "Host Options:\n");
  20   fprintf(stderr, "  -p <n>             Simulate <n> processors [default 1]\n");
  21   fprintf(stderr, "  -m <n>             Provide <n> MiB of target memory [default 4096]\n");
  22   fprintf(stderr, "  -d                 Interactive debug mode\n");
  23   fprintf(stderr, "  -g                 Track histogram of PCs\n");
  24   fprintf(stderr, "  -h                 Print this help message\n");
  25   fprintf(stderr, "  --isa=<name>       RISC-V ISA string [default RV64IMAFDC]\n");
  26   fprintf(stderr, "  --ic=<S>:<W>:<B>   Instantiate a cache model with S sets,\n");
  27   fprintf(stderr, "  --dc=<S>:<W>:<B>     W ways, and B-byte blocks (with S and\n");
  28   fprintf(stderr, "  --l2=<S>:<W>:<B>     B both powers of 2).\n");
  29   fprintf(stderr, "  --extension=<name> Specify RoCC Extension\n");
  30   fprintf(stderr, "  --extlib=<name>    Shared library to load\n");
  31   exit(1);
  32 }
  33
  34 int main(int argc, char** argv)
  35 {
  36   bool debug = false;
  37   bool histogram = false;
  38   size_t nprocs = 1;
  39   size_t mem_mb = 0;
  40   std::unique_ptr<icache_sim_t> ic;
  41   std::unique_ptr<dcache_sim_t> dc;
  42   std::unique_ptr<cache_sim_t> l2;
  43   std::function<extension_t*()> extension;
  44   const char* isa = "RV64";
  45
  46   option_parser_t parser;
  47   parser.help(&help);
  48   parser.option('h', 0, 0, [&](const char* s){help();});
  49   parser.option('d', 0, 0, [&](const char* s){debug = true;});
  50   parser.option('g', 0, 0, [&](const char* s){histogram = true;});
  51   parser.option('p', 0, 1, [&](const char* s){nprocs = atoi(s);});
  52   parser.option('m', 0, 1, [&](const char* s){mem_mb = atoi(s);});
  53   parser.option(0, "ic", 1, [&](const char* s){ic.reset(new icache_sim_t(s));});
  54   parser.option(0, "dc", 1, [&](const char* s){dc.reset(new dcache_sim_t(s));});
  55   parser.option(0, "l2", 1, [&](const char* s){l2.reset(cache_sim_t::construct(s, "L2$"));});
  56   parser.option(0, "isa", 1, [&](const char* s){isa = s;});
  57   parser.option(0, "extension", 1, [&](const char* s){extension = find_extension(s);});
  58   parser.option(0, "extlib", 1, [&](const char *s){
  59     void *lib = dlopen(s, RTLD_NOW | RTLD_GLOBAL);
  60     if (lib == NULL) {
  61       fprintf(stderr, "Unable to load extlib '%s': %s\n", s, dlerror());
  62       exit(-1);
  63     }
  64   });
  65
  66   auto argv1 = parser.parse(argv);
  67   if (!*argv1)
  68     help();
  69   std::vector<std::string> htif_args(argv1, (const char*const*)argv + argc);
  70   sim_t s(isa, nprocs, mem_mb, htif_args);
  71
  72   if (ic && l2) ic->set_miss_handler(&*l2);
  73   if (dc && l2) dc->set_miss_handler(&*l2);
  74   for (size_t i = 0; i < nprocs; i++)
  75   {
  76     if (ic) s.get_core(i)->get_mmu()->register_memtracer(&*ic);
  77     if (dc) s.get_core(i)->get_mmu()->register_memtracer(&*dc);
  78     if (extension) s.get_core(i)->register_extension(extension());
  79   }
  80
  81   s.set_debug(debug);
  82   s.set_histogram(histogram);
  83   return s.run();
  84 }