b7748d6bd098bdc5720ae1ea1d5e8a8f21f4e22a
[riscv-isa-sim.git] / spike_main / spike.cc
1 // See LICENSE for license details.
2
3 #include "sim.h"
4 #include "mmu.h"
5 #include "gdbserver.h"
6 #include "htif.h"
7 #include "cachesim.h"
8 #include "extension.h"
9 #include <dlfcn.h>
10 #include <fesvr/option_parser.h>
11 #include <stdio.h>
12 #include <stdlib.h>
13 #include <getopt.h>
14 #include <vector>
15 #include <string>
16 #include <memory>
17
18 static void help()
19 {
20 fprintf(stderr, "usage: spike [host options] <target program> [target options]\n");
21 fprintf(stderr, "Host Options:\n");
22 fprintf(stderr, " -p<n> Simulate <n> processors [default 1]\n");
23 fprintf(stderr, " -m<n> Provide <n> MiB of target memory [default 4096]\n");
24 fprintf(stderr, " -d Interactive debug mode\n");
25 fprintf(stderr, " -g Track histogram of PCs\n");
26 fprintf(stderr, " -l Generate a log of execution\n");
27 fprintf(stderr, " -h Print this help message\n");
28 fprintf(stderr, " --isa=<name> RISC-V ISA string [default %s]\n", DEFAULT_ISA);
29 fprintf(stderr, " --ic=<S>:<W>:<B> Instantiate a cache model with S sets,\n");
30 fprintf(stderr, " --dc=<S>:<W>:<B> W ways, and B-byte blocks (with S and\n");
31 fprintf(stderr, " --l2=<S>:<W>:<B> B both powers of 2).\n");
32 fprintf(stderr, " --extension=<name> Specify RoCC Extension\n");
33 fprintf(stderr, " --extlib=<name> Shared library to load\n");
34 fprintf(stderr, " --dump-config-string Print platform configuration string and exit\n");
35 exit(1);
36 }
37
38 int main(int argc, char** argv)
39 {
40 bool debug = false;
41 bool histogram = false;
42 bool log = false;
43 bool dump_config_string = false;
44 size_t nprocs = 1;
45 size_t mem_mb = 0;
46 std::unique_ptr<icache_sim_t> ic;
47 std::unique_ptr<dcache_sim_t> dc;
48 std::unique_ptr<cache_sim_t> l2;
49 std::function<extension_t*()> extension;
50 const char* isa = DEFAULT_ISA;
51
52 option_parser_t parser;
53 parser.help(&help);
54 parser.option('h', 0, 0, [&](const char* s){help();});
55 parser.option('d', 0, 0, [&](const char* s){debug = true;});
56 parser.option('g', 0, 0, [&](const char* s){histogram = true;});
57 parser.option('l', 0, 0, [&](const char* s){log = true;});
58 parser.option('p', 0, 1, [&](const char* s){nprocs = atoi(s);});
59 parser.option('m', 0, 1, [&](const char* s){mem_mb = atoi(s);});
60 parser.option(0, "ic", 1, [&](const char* s){ic.reset(new icache_sim_t(s));});
61 parser.option(0, "dc", 1, [&](const char* s){dc.reset(new dcache_sim_t(s));});
62 parser.option(0, "l2", 1, [&](const char* s){l2.reset(cache_sim_t::construct(s, "L2$"));});
63 parser.option(0, "isa", 1, [&](const char* s){isa = s;});
64 parser.option(0, "extension", 1, [&](const char* s){extension = find_extension(s);});
65 parser.option(0, "dump-config-string", 0, [&](const char *s){dump_config_string = true;});
66 parser.option(0, "extlib", 1, [&](const char *s){
67 void *lib = dlopen(s, RTLD_NOW | RTLD_GLOBAL);
68 if (lib == NULL) {
69 fprintf(stderr, "Unable to load extlib '%s': %s\n", s, dlerror());
70 exit(-1);
71 }
72 });
73
74 auto argv1 = parser.parse(argv);
75 std::vector<std::string> htif_args(argv1, (const char*const*)argv + argc);
76 sim_t s(isa, nprocs, mem_mb, htif_args);
77 gdbserver_t gdbserver(9824);
78 s.set_gdbserver(&gdbserver);
79
80 if (dump_config_string) {
81 printf("%s", s.get_config_string());
82 return 0;
83 }
84
85 if (!*argv1)
86 help();
87
88 if (ic && l2) ic->set_miss_handler(&*l2);
89 if (dc && l2) dc->set_miss_handler(&*l2);
90 for (size_t i = 0; i < nprocs; i++)
91 {
92 if (ic) s.get_core(i)->get_mmu()->register_memtracer(&*ic);
93 if (dc) s.get_core(i)->get_mmu()->register_memtracer(&*dc);
94 if (extension) s.get_core(i)->register_extension(extension());
95 }
96
97 s.set_debug(debug);
98 s.set_log(log);
99 s.set_histogram(histogram);
100 return s.run();
101 }