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Update README
[riscv-isa-sim.git]
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README.md
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README.md
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-RISC-V ISA Simulator
-======================
-
-Author : Andrew Waterman, Yunsup Lee
-
-Date : June 19, 2011
-
-Version : (under version control)
+Spike RISC-V ISA Simulator
+============================
About
-------------
About
-------------
-
The RISC-V ISA Simulator
implements a functional model of one or more
+
Spike, the RISC-V ISA Simulator,
implements a functional model of one or more
RISC-V processors.
RISC-V processors.
+Spike is named after the golden spike used to celebrate the completion of the
+US transcontinental railway.
+
Build Steps
---------------
Build Steps
---------------