Merge pull request #117 from riscv/multicore_debug

[riscv-isa-sim.git] / config.h.in

diff --git a/config.h.in b/config.h.in
index 15b5850defa329b48c47ef2f55c6f8f0c2bd7b71..137f1950054e3e4b709a76233c2aadcee778c7cf 100644 (file)
--- a/config.h.in
+++ b/config.h.in
@@ -75,6 +75,9 @@
 /* Enable PC histogram generation */
 #undef RISCV_ENABLE_HISTOGRAM
 
+/* Enable hardware support for misaligned loads and stores */
+#undef RISCV_ENABLE_MISALIGNED
+
 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
 #undef SOFTFLOAT_ENABLED