Merge pull request #117 from riscv/multicore_debug

[riscv-isa-sim.git] / config.h.in

diff --git a/config.h.in b/config.h.in
index 2ec49115309bf6bee29e1f075b009536a839d7de..137f1950054e3e4b709a76233c2aadcee778c7cf 100644 (file)
--- a/config.h.in
+++ b/config.h.in
@@ -1,11 +1,50 @@
 /* config.h.in.  Generated from configure.ac by autoheader.  */
 
+/* Define if building universal (internal helper macro) */
+#undef AC_APPLE_UNIVERSAL_BUILD
+
+/* Default value for --isa switch */
+#undef DEFAULT_ISA
+
+/* Path to the device-tree-compiler */
+#undef DTC
+
+/* Define if subproject MCPPBS_SPROJ_NORM is enabled */
+#undef DUMMY_ROCC_ENABLED
+
+/* Define to 1 if you have the <inttypes.h> header file. */
+#undef HAVE_INTTYPES_H
+
 /* Define to 1 if you have the `fesvr' library (-lfesvr). */
 #undef HAVE_LIBFESVR
 
 /* Define to 1 if you have the `pthread' library (-lpthread). */
 #undef HAVE_LIBPTHREAD
 
+/* Define to 1 if you have the <memory.h> header file. */
+#undef HAVE_MEMORY_H
+
+/* Define to 1 if you have the <stdint.h> header file. */
+#undef HAVE_STDINT_H
+
+/* Define to 1 if you have the <stdlib.h> header file. */
+#undef HAVE_STDLIB_H
+
+/* Define to 1 if you have the <strings.h> header file. */
+#undef HAVE_STRINGS_H
+
+/* Define to 1 if you have the <string.h> header file. */
+#undef HAVE_STRING_H
+
+/* Define to 1 if you have the <sys/stat.h> header file. */
+#undef HAVE_SYS_STAT_H
+
+/* Define to 1 if you have the <sys/types.h> header file. */
+#undef HAVE_SYS_TYPES_H
+
+/* Define to 1 if you have the <unistd.h> header file. */
+#undef HAVE_UNISTD_H
+
 /* Define to the address where bug reports for this package should be sent. */
 #undef PACKAGE_BUGREPORT
 
@@ -27,17 +66,35 @@
 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
 #undef RISCV_ENABLED
 
-/* Define if 64-bit mode is supported */
-#undef RISCV_ENABLE_64BIT
+/* Enable commit log generation */
+#undef RISCV_ENABLE_COMMITLOG
+
+/* Enable hardware management of PTE accessed and dirty bits */
+#undef RISCV_ENABLE_DIRTY
 
-/* Define if floating-point instructions are supported */
-#undef RISCV_ENABLE_FPU
+/* Enable PC histogram generation */
+#undef RISCV_ENABLE_HISTOGRAM
+
+/* Enable hardware support for misaligned loads and stores */
+#undef RISCV_ENABLE_MISALIGNED
 
 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
 #undef SOFTFLOAT_ENABLED
 
 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
-#undef SOFTFLOAT_RISCV_ENABLED
+#undef SPIKE_MAIN_ENABLED
 
 /* Define to 1 if you have the ANSI C header files. */
 #undef STDC_HEADERS
+
+/* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most
+   significant byte first (like Motorola and SPARC, unlike Intel). */
+#if defined AC_APPLE_UNIVERSAL_BUILD
+# if defined __BIG_ENDIAN__
+#  define WORDS_BIGENDIAN 1
+# endif
+#else
+# ifndef WORDS_BIGENDIAN
+#  undef WORDS_BIGENDIAN
+# endif
+#endif