Implement RVC draft

[riscv-isa-sim.git] / config.h.in

diff --git a/config.h.in b/config.h.in
index 52c725334ffdea85adc4ba99a916becf33cd8e7c..5293fa8dafc9121be87a0d46ab089f0402964547 100644 (file)
--- a/config.h.in
+++ b/config.h.in
@@ -45,6 +45,9 @@
 /* Enable PC histogram generation */
 #undef RISCV_ENABLE_HISTOGRAM
 
+/* Define if RISC-V Compressed is supported */
+#undef RISCV_ENABLE_RVC
+
 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
 #undef SOFTFLOAT_ENABLED