#include "debug_rom/debug_rom.h"
#include "debug_rom/debug_rom_defines.h"
-#if 0
+#if 1
# define D(x) x
#else
# define D(x)
///////////////////////// debug_module_t
-debug_module_t::debug_module_t(sim_t *sim, unsigned progbufsize) :
+debug_module_t::debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bus_master_bits) :
progbufsize(progbufsize),
program_buffer_bytes(4 + 4*progbufsize),
+ max_bus_master_bits(max_bus_master_bits),
debug_progbuf_start(debug_data_start - program_buffer_bytes),
debug_abstract_start(debug_progbuf_start - debug_abstract_size*4),
sim(sim)
{
+ D(fprintf(stderr, "debug_data_start=0x%x\n", debug_data_start));
+ D(fprintf(stderr, "debug_progbuf_start=0x%x\n", debug_progbuf_start));
+ D(fprintf(stderr, "debug_abstract_start=0x%x\n", debug_abstract_start));
+
program_buffer = new uint8_t[program_buffer_bytes];
memset(halted, 0, sizeof(halted));
abstractauto = {0};
sbcs = {0};
- sbcs.version = 1;
- sbcs.access64 = true;
- sbcs.access32 = true;
- sbcs.access16 = true;
- sbcs.access8 = true;
- sbcs.asize = sizeof(reg_t) * 8;
+ if (max_bus_master_bits > 0) {
+ sbcs.version = 1;
+ sbcs.asize = sizeof(reg_t) * 8;
+ }
+ if (max_bus_master_bits >= 64)
+ sbcs.access64 = true;
+ if (max_bus_master_bits >= 32)
+ sbcs.access32 = true;
+ if (max_bus_master_bits >= 16)
+ sbcs.access16 = true;
+ if (max_bus_master_bits >= 8)
+ sbcs.access8 = true;
}
void debug_module_t::add_device(bus_t *bus) {
void debug_module_t::sb_autoincrement()
{
- if (!sbcs.autoincrement)
+ if (!sbcs.autoincrement || !max_bus_master_bits)
return;
uint64_t value = sbaddress[0] + sb_access_bits() / 8;
void debug_module_t::sb_read()
{
reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0];
- D(fprintf(stderr, "sb_read() @ 0x%lx\n", address));
try {
- switch (sbcs.sbaccess) {
- case 0:
- sbdata[0] = sim->debug_mmu->load_uint8(address);
- break;
- case 1:
- sbdata[0] = sim->debug_mmu->load_uint16(address);
- break;
- case 2:
- sbdata[0] = sim->debug_mmu->load_uint32(address);
- D(fprintf(stderr, " -> 0x%x\n", sbdata[0]));
- break;
- case 3:
- {
- uint64_t value = sim->debug_mmu->load_uint32(address);
- sbdata[0] = value;
- sbdata[1] = value >> 32;
- break;
- }
- default:
- sbcs.error = 3;
- break;
+ if (sbcs.sbaccess == 0 && max_bus_master_bits >= 8) {
+ sbdata[0] = sim->debug_mmu->load_uint8(address);
+ } else if (sbcs.sbaccess == 1 && max_bus_master_bits >= 16) {
+ sbdata[0] = sim->debug_mmu->load_uint16(address);
+ } else if (sbcs.sbaccess == 2 && max_bus_master_bits >= 32) {
+ sbdata[0] = sim->debug_mmu->load_uint32(address);
+ } else if (sbcs.sbaccess == 3 && max_bus_master_bits >= 64) {
+ uint64_t value = sim->debug_mmu->load_uint32(address);
+ sbdata[0] = value;
+ sbdata[1] = value >> 32;
+ } else {
+ sbcs.error = 3;
}
} catch (trap_load_access_fault& t) {
sbcs.error = 2;
{
reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0];
D(fprintf(stderr, "sb_write() 0x%x @ 0x%lx\n", sbdata[0], address));
- switch (sbcs.sbaccess) {
- case 0:
- sim->debug_mmu->store_uint8(address, sbdata[0]);
- break;
- case 1:
- sim->debug_mmu->store_uint16(address, sbdata[0]);
- break;
- case 2:
- sim->debug_mmu->store_uint32(address, sbdata[0]);
- break;
- case 3:
- sim->debug_mmu->store_uint64(address,
- (((uint64_t) sbdata[1]) << 32) | sbdata[0]);
- break;
- default:
- sbcs.error = 3;
- break;
+ if (sbcs.sbaccess == 0 && max_bus_master_bits >= 8) {
+ sim->debug_mmu->store_uint8(address, sbdata[0]);
+ } else if (sbcs.sbaccess == 1 && max_bus_master_bits >= 16) {
+ sim->debug_mmu->store_uint16(address, sbdata[0]);
+ } else if (sbcs.sbaccess == 2 && max_bus_master_bits >= 32) {
+ sim->debug_mmu->store_uint32(address, sbdata[0]);
+ } else if (sbcs.sbaccess == 3 && max_bus_master_bits >= 64) {
+ sim->debug_mmu->store_uint64(address,
+ (((uint64_t) sbdata[1]) << 32) | sbdata[0]);
+ } else {
+ sbcs.error = 3;
}
}
result = set_field(result, DMI_DMCONTROL_HALTREQ, dmcontrol.haltreq);
result = set_field(result, DMI_DMCONTROL_RESUMEREQ, dmcontrol.resumereq);
- result = set_field(result, DMI_DMCONTROL_HARTSEL, dmcontrol.hartsel);
+ result = set_field(result, ((1L<<hartsellen)-1) <<
+ DMI_DMCONTROL_HARTSEL_OFFSET, dmcontrol.hartsel);
result = set_field(result, DMI_DMCONTROL_HARTRESET, dmcontrol.hartreset);
result = set_field(result, DMI_DMCONTROL_NDMRESET, dmcontrol.ndmreset);
result = set_field(result, DMI_DMCONTROL_DMACTIVE, dmcontrol.dmactive);
result = set_field(result, DMI_HARTINFO_DATAADDR, debug_data_start);
break;
case DMI_SBCS:
- result = set_field(result, DMI_SBCS_VERSION, sbcs.version);
+ result = set_field(result, DMI_SBCS_SBVERSION, sbcs.version);
result = set_field(result, DMI_SBCS_SBREADONADDR, sbcs.readonaddr);
result = set_field(result, DMI_SBCS_SBACCESS, sbcs.sbaccess);
result = set_field(result, DMI_SBCS_SBAUTOINCREMENT, sbcs.autoincrement);
return true;
}
+ D(fprintf(stderr, ">>> perform_abstract_command(0x%x)\n", command));
+
if ((command >> 24) == 0) {
// register access
unsigned size = get_field(command, AC_ACCESS_REGISTER_SIZE);
if (get_field(command, AC_ACCESS_REGISTER_TRANSFER)) {
- if (regno < 0x1000 || regno >= 0x1020) {
- abstractcs.cmderr = CMDERR_NOTSUP;
- return true;
- }
-
- unsigned regnum = regno - 0x1000;
+ if (regno >= 0x1000 && regno < 0x1020) {
+ unsigned regnum = regno - 0x1000;
+
+ switch (size) {
+ case 2:
+ if (write)
+ write32(debug_abstract, 0, lw(regnum, ZERO, debug_data_start));
+ else
+ write32(debug_abstract, 0, sw(regnum, ZERO, debug_data_start));
+ break;
+ case 3:
+ if (write)
+ write32(debug_abstract, 0, ld(regnum, ZERO, debug_data_start));
+ else
+ write32(debug_abstract, 0, sd(regnum, ZERO, debug_data_start));
+ break;
+ default:
+ abstractcs.cmderr = CMDERR_NOTSUP;
+ return true;
+ }
- switch (size) {
- case 2:
- if (write)
- write32(debug_abstract, 0, lw(regnum, ZERO, debug_data_start));
- else
- write32(debug_abstract, 0, sw(regnum, ZERO, debug_data_start));
- break;
- case 3:
- if (write)
- write32(debug_abstract, 0, ld(regnum, ZERO, debug_data_start));
- else
- write32(debug_abstract, 0, sd(regnum, ZERO, debug_data_start));
- break;
- /*
- case 4:
- if (write)
- write32(debug_rom_code, 0, lq(regnum, ZERO, debug_data_start));
- else
- write32(debug_rom_code, 0, sq(regnum, ZERO, debug_data_start));
- break;
- */
- default:
+ } else {
abstractcs.cmderr = CMDERR_NOTSUP;
return true;
}
- } else {
- //NOP
- write32(debug_abstract, 0, addi(ZERO, ZERO, 0));
- }
- if (get_field(command, AC_ACCESS_REGISTER_POSTEXEC)) {
- // Since the next instruction is what we will use, just use nother NOP
- // to get there.
- write32(debug_abstract, 1, addi(ZERO, ZERO, 0));
- } else {
- write32(debug_abstract, 1, ebreak());
+ if (get_field(command, AC_ACCESS_REGISTER_POSTEXEC)) {
+ D(fprintf(stderr, ">>> post-exec!\n"));
+ write32(debug_abstract, 1,
+ jal(ZERO, debug_progbuf_start - debug_abstract_start - 4));
+ } else {
+ write32(debug_abstract, 1, ebreak());
+ }
}
debug_rom_flags[dmcontrol.hartsel] |= 1 << DEBUG_ROM_FLAG_GO;
dmcontrol.resumereq = get_field(value, DMI_DMCONTROL_RESUMEREQ);
dmcontrol.hartreset = get_field(value, DMI_DMCONTROL_HARTRESET);
dmcontrol.ndmreset = get_field(value, DMI_DMCONTROL_NDMRESET);
- dmcontrol.hartsel = get_field(value, DMI_DMCONTROL_HARTSEL);
+ dmcontrol.hartsel = get_field(value, ((1L<<hartsellen)-1) <<
+ DMI_DMCONTROL_HARTSEL_OFFSET);
}
processor_t *proc = current_proc();
if (proc) {
projects / riscv-isa-sim.git / blobdiff