#include "debug_defines.h"
#include "opcodes.h"
#include "mmu.h"
+#include "sim.h"
#include "debug_rom/debug_rom.h"
-#include "debug_rom/debug_rom_defines.h"
+#include "debug_rom_defines.h"
#if 0
# define D(x) x
///////////////////////// debug_module_t
-debug_module_t::debug_module_t(sim_t *sim, unsigned progbufsize) :
+debug_module_t::debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bus_master_bits,
+ bool require_authentication) :
progbufsize(progbufsize),
program_buffer_bytes(4 + 4*progbufsize),
+ max_bus_master_bits(max_bus_master_bits),
+ require_authentication(require_authentication),
debug_progbuf_start(debug_data_start - program_buffer_bytes),
debug_abstract_start(debug_progbuf_start - debug_abstract_size*4),
sim(sim)
{
+ D(fprintf(stderr, "debug_data_start=0x%x\n", debug_data_start));
+ D(fprintf(stderr, "debug_progbuf_start=0x%x\n", debug_progbuf_start));
+ D(fprintf(stderr, "debug_abstract_start=0x%x\n", debug_abstract_start));
+
program_buffer = new uint8_t[program_buffer_bytes];
memset(halted, 0, sizeof(halted));
memset(debug_rom_flags, 0, sizeof(debug_rom_flags));
memset(resumeack, 0, sizeof(resumeack));
+ memset(havereset, 0, sizeof(havereset));
memset(program_buffer, 0, program_buffer_bytes);
program_buffer[4*progbufsize] = ebreak();
program_buffer[4*progbufsize+1] = ebreak() >> 8;
dmstatus = {0};
dmstatus.impebreak = true;
- dmstatus.authenticated = 1;
+ dmstatus.authenticated = !require_authentication;
dmstatus.version = 2;
abstractcs = {0};
abstractauto = {0};
sbcs = {0};
- sbcs.version = 1;
- sbcs.access64 = true;
- sbcs.access32 = true;
- sbcs.access16 = true;
- sbcs.access8 = true;
- sbcs.asize = sizeof(reg_t) * 8;
+ if (max_bus_master_bits > 0) {
+ sbcs.version = 1;
+ sbcs.asize = sizeof(reg_t) * 8;
+ }
+ if (max_bus_master_bits >= 64)
+ sbcs.access64 = true;
+ if (max_bus_master_bits >= 32)
+ sbcs.access32 = true;
+ if (max_bus_master_bits >= 16)
+ sbcs.access16 = true;
+ if (max_bus_master_bits >= 8)
+ sbcs.access8 = true;
+
+ challenge = random();
}
void debug_module_t::add_device(bus_t *bus) {
void debug_module_t::sb_autoincrement()
{
- if (!sbcs.autoincrement)
+ if (!sbcs.autoincrement || !max_bus_master_bits)
return;
uint64_t value = sbaddress[0] + sb_access_bits() / 8;
void debug_module_t::sb_read()
{
reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0];
- D(fprintf(stderr, "sb_read() @ 0x%lx\n", address));
try {
- switch (sbcs.sbaccess) {
- case 0:
- sbdata[0] = sim->debug_mmu->load_uint8(address);
- break;
- case 1:
- sbdata[0] = sim->debug_mmu->load_uint16(address);
- break;
- case 2:
- sbdata[0] = sim->debug_mmu->load_uint32(address);
- D(fprintf(stderr, " -> 0x%x\n", sbdata[0]));
- break;
- case 3:
- {
- uint64_t value = sim->debug_mmu->load_uint32(address);
- sbdata[0] = value;
- sbdata[1] = value >> 32;
- break;
- }
- default:
- sbcs.error = 3;
- break;
+ if (sbcs.sbaccess == 0 && max_bus_master_bits >= 8) {
+ sbdata[0] = sim->debug_mmu->load_uint8(address);
+ } else if (sbcs.sbaccess == 1 && max_bus_master_bits >= 16) {
+ sbdata[0] = sim->debug_mmu->load_uint16(address);
+ } else if (sbcs.sbaccess == 2 && max_bus_master_bits >= 32) {
+ sbdata[0] = sim->debug_mmu->load_uint32(address);
+ } else if (sbcs.sbaccess == 3 && max_bus_master_bits >= 64) {
+ uint64_t value = sim->debug_mmu->load_uint32(address);
+ sbdata[0] = value;
+ sbdata[1] = value >> 32;
+ } else {
+ sbcs.error = 3;
}
} catch (trap_load_access_fault& t) {
sbcs.error = 2;
{
reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0];
D(fprintf(stderr, "sb_write() 0x%x @ 0x%lx\n", sbdata[0], address));
- switch (sbcs.sbaccess) {
- case 0:
- sim->debug_mmu->store_uint8(address, sbdata[0]);
- break;
- case 1:
- sim->debug_mmu->store_uint16(address, sbdata[0]);
- break;
- case 2:
- sim->debug_mmu->store_uint32(address, sbdata[0]);
- break;
- case 3:
- sim->debug_mmu->store_uint64(address,
- (((uint64_t) sbdata[1]) << 32) | sbdata[0]);
- break;
- default:
- sbcs.error = 3;
- break;
+ if (sbcs.sbaccess == 0 && max_bus_master_bits >= 8) {
+ sim->debug_mmu->store_uint8(address, sbdata[0]);
+ } else if (sbcs.sbaccess == 1 && max_bus_master_bits >= 16) {
+ sim->debug_mmu->store_uint16(address, sbdata[0]);
+ } else if (sbcs.sbaccess == 2 && max_bus_master_bits >= 32) {
+ sim->debug_mmu->store_uint32(address, sbdata[0]);
+ } else if (sbcs.sbaccess == 3 && max_bus_master_bits >= 64) {
+ sim->debug_mmu->store_uint64(address,
+ (((uint64_t) sbdata[1]) << 32) | sbdata[0]);
+ } else {
+ sbcs.error = 3;
}
}
result = set_field(result, DMI_DMSTATUS_IMPEBREAK,
dmstatus.impebreak);
+ result = set_field(result, DMI_DMSTATUS_ALLHAVERESET,
+ havereset[dmcontrol.hartsel]);
+ result = set_field(result, DMI_DMSTATUS_ANYHAVERESET,
+ havereset[dmcontrol.hartsel]);
result = set_field(result, DMI_DMSTATUS_ALLNONEXISTENT, dmstatus.allnonexistant);
result = set_field(result, DMI_DMSTATUS_ALLUNAVAIL, dmstatus.allunavail);
result = set_field(result, DMI_DMSTATUS_ALLRUNNING, dmstatus.allrunning);
case DMI_SBDATA3:
result = sbdata[3];
break;
+ case DMI_AUTHDATA:
+ result = challenge;
+ break;
default:
result = 0;
D(fprintf(stderr, "Unexpected. Returning Error."));
return true;
}
+ unsigned i = 0;
if (get_field(command, AC_ACCESS_REGISTER_TRANSFER)) {
- if (regno < 0x1000 || regno >= 0x1020) {
- abstractcs.cmderr = CMDERR_NOTSUP;
- return true;
- }
+ if (regno < 0x1000 && progbufsize < 2) {
+ // Make the debugger use the program buffer if it's available, so it
+ // can test both use cases.
+ write32(debug_abstract, i++, csrw(S0, CSR_DSCRATCH));
+
+ if (write) {
+ switch (size) {
+ case 2:
+ write32(debug_abstract, i++, lw(S0, ZERO, debug_data_start));
+ break;
+ case 3:
+ write32(debug_abstract, i++, ld(S0, ZERO, debug_data_start));
+ break;
+ default:
+ abstractcs.cmderr = CMDERR_NOTSUP;
+ return true;
+ }
+ write32(debug_abstract, i++, csrw(S0, regno));
+
+ } else {
+ write32(debug_abstract, i++, csrr(S0, regno));
+ switch (size) {
+ case 2:
+ write32(debug_abstract, i++, sw(S0, ZERO, debug_data_start));
+ break;
+ case 3:
+ write32(debug_abstract, i++, sd(S0, ZERO, debug_data_start));
+ break;
+ default:
+ abstractcs.cmderr = CMDERR_NOTSUP;
+ return true;
+ }
+ }
+ write32(debug_abstract, i++, csrr(S0, CSR_DSCRATCH));
+
+ } else if (regno >= 0x1000 && regno < 0x1020) {
+ unsigned regnum = regno - 0x1000;
+
+ switch (size) {
+ case 2:
+ if (write)
+ write32(debug_abstract, i++, lw(regnum, ZERO, debug_data_start));
+ else
+ write32(debug_abstract, i++, sw(regnum, ZERO, debug_data_start));
+ break;
+ case 3:
+ if (write)
+ write32(debug_abstract, i++, ld(regnum, ZERO, debug_data_start));
+ else
+ write32(debug_abstract, i++, sd(regnum, ZERO, debug_data_start));
+ break;
+ default:
+ abstractcs.cmderr = CMDERR_NOTSUP;
+ return true;
+ }
- unsigned regnum = regno - 0x1000;
+ } else if (regno >= 0x1020 && regno < 0x1040) {
+ // Don't force the debugger to use progbuf if it exists, so the
+ // debugger has to make the decision not to use abstract commands to
+ // access 64-bit FPRs on 32-bit targets.
+ unsigned fprnum = regno - 0x1020;
+
+ if (write) {
+ switch (size) {
+ case 2:
+ write32(debug_abstract, i++, flw(fprnum, ZERO, debug_data_start));
+ break;
+ case 3:
+ write32(debug_abstract, i++, fld(fprnum, ZERO, debug_data_start));
+ break;
+ default:
+ abstractcs.cmderr = CMDERR_NOTSUP;
+ return true;
+ }
- switch (size) {
- case 2:
- if (write)
- write32(debug_abstract, 0, lw(regnum, ZERO, debug_data_start));
- else
- write32(debug_abstract, 0, sw(regnum, ZERO, debug_data_start));
- break;
- case 3:
- if (write)
- write32(debug_abstract, 0, ld(regnum, ZERO, debug_data_start));
- else
- write32(debug_abstract, 0, sd(regnum, ZERO, debug_data_start));
- break;
- /*
- case 4:
- if (write)
- write32(debug_rom_code, 0, lq(regnum, ZERO, debug_data_start));
- else
- write32(debug_rom_code, 0, sq(regnum, ZERO, debug_data_start));
- break;
- */
- default:
+ } else {
+ switch (size) {
+ case 2:
+ write32(debug_abstract, i++, fsw(fprnum, ZERO, debug_data_start));
+ break;
+ case 3:
+ write32(debug_abstract, i++, fsd(fprnum, ZERO, debug_data_start));
+ break;
+ default:
+ abstractcs.cmderr = CMDERR_NOTSUP;
+ return true;
+ }
+ }
+
+ } else {
abstractcs.cmderr = CMDERR_NOTSUP;
return true;
}
- } else {
- //NOP
- write32(debug_abstract, 0, addi(ZERO, ZERO, 0));
}
if (get_field(command, AC_ACCESS_REGISTER_POSTEXEC)) {
- // Since the next instruction is what we will use, just use nother NOP
- // to get there.
- write32(debug_abstract, 1, addi(ZERO, ZERO, 0));
+ write32(debug_abstract, i,
+ jal(ZERO, debug_progbuf_start - debug_abstract_start - 4 * i));
+ i++;
} else {
- write32(debug_abstract, 1, ebreak());
+ write32(debug_abstract, i++, ebreak());
}
debug_rom_flags[dmcontrol.hartsel] |= 1 << DEBUG_ROM_FLAG_GO;
bool debug_module_t::dmi_write(unsigned address, uint32_t value)
{
D(fprintf(stderr, "dmi_write(0x%x, 0x%x)\n", address, value));
+
+ if (!dmstatus.authenticated && address != DMI_AUTHDATA &&
+ address != DMI_DMCONTROL)
+ return false;
+
if (address >= DMI_DATA0 && address < DMI_DATA0 + abstractcs.datacount) {
unsigned i = address - DMI_DATA0;
if (!abstractcs.busy)
if (!dmcontrol.dmactive && get_field(value, DMI_DMCONTROL_DMACTIVE))
reset();
dmcontrol.dmactive = get_field(value, DMI_DMCONTROL_DMACTIVE);
+ if (!dmstatus.authenticated)
+ return true;
if (dmcontrol.dmactive) {
dmcontrol.haltreq = get_field(value, DMI_DMCONTROL_HALTREQ);
dmcontrol.resumereq = get_field(value, DMI_DMCONTROL_RESUMEREQ);
dmcontrol.ndmreset = get_field(value, DMI_DMCONTROL_NDMRESET);
dmcontrol.hartsel = get_field(value, ((1L<<hartsellen)-1) <<
DMI_DMCONTROL_HARTSEL_OFFSET);
+ if (get_field(value, DMI_DMCONTROL_ACKHAVERESET)) {
+ havereset[dmcontrol.hartsel] = false;
+ }
}
processor_t *proc = current_proc();
if (proc) {
case DMI_SBDATA3:
sbdata[3] = value;
return true;
+ case DMI_AUTHDATA:
+ D(fprintf(stderr, "debug authentication: got 0x%x; 0x%x unlocks\n", value,
+ challenge + secret));
+ if (require_authentication) {
+ if (value == challenge + secret) {
+ dmstatus.authenticated = true;
+ } else {
+ dmstatus.authenticated = false;
+ challenge = random();
+ }
+ }
+ return true;
}
}
return false;
}
+
+void debug_module_t::proc_reset(unsigned id)
+{
+ havereset[id] = true;
+ halted[id] = false;
+}
projects / riscv-isa-sim.git / blobdiff