Implement resume (untested).

[riscv-isa-sim.git] / riscv / debug_module.h

diff --git a/riscv/debug_module.h b/riscv/debug_module.h
index fdeaaaccb86c8518f5029fab989ca97739393f3d..7d9b3aa646bed3a9534017a9e8ed90a0255f5769 100644 (file)
--- a/riscv/debug_module.h
+++ b/riscv/debug_module.h
@@ -10,6 +10,7 @@ class sim_t;
 
 typedef struct {
   bool haltreq;
+  bool resumereq;
   bool reset;
   bool dmactive;
   enum {