Move towards RVC v1.8

[riscv-isa-sim.git] / riscv / decode.h

diff --git a/riscv/decode.h b/riscv/decode.h
index 91ad73ee593e9b598c7204681f679bef22b9d569..16e57d72353a1c7657491c4e887acff5e1e29b19 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -89,7 +89,6 @@ public:
   uint64_t rvc_rd() { return rd(); }
   uint64_t rvc_rs1() { return rd(); }
   uint64_t rvc_rs2() { return x(2, 5); }
-  uint64_t rvc_rds() { return 8 + x(10, 3); }
   uint64_t rvc_rs1s() { return 8 + x(7, 3); }
   uint64_t rvc_rs2s() { return 8 + x(2, 3); }
 private:
@@ -122,26 +121,33 @@ private:
 #define READ_REG(reg) STATE.XPR[reg]
 #define RS1 READ_REG(insn.rs1())
 #define RS2 READ_REG(insn.rs2())
-#define WRITE_REG(reg, value) STATE.XPR.write(reg, value)
 #define WRITE_RD(value) WRITE_REG(insn.rd(), value)
 
-#ifdef RISCV_ENABLE_COMMITLOG
-  #undef WRITE_REG
-  #define WRITE_REG(reg, value) ({ \
-        reg_t wdata = (value); /* value is a func with side-effects */ \
-        STATE.log_reg_write = (commit_log_reg_t){(reg) << 1, wdata}; \
-        STATE.XPR.write(reg, wdata); \
-      })
+#ifndef RISCV_ENABLE_COMMITLOG
+# define WRITE_REG(reg, value) STATE.XPR.write(reg, value)
+# define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, value)
+#else
+# define WRITE_REG(reg, value) ({ \
+    reg_t wdata = (value); /* value may have side effects */ \
+    STATE.log_reg_write = (commit_log_reg_t){(reg) << 1, wdata}; \
+    STATE.XPR.write(reg, wdata); \
+  })
+# define WRITE_FREG(reg, value) ({ \
+    freg_t wdata = (value); /* value may have side effects */ \
+    STATE.log_reg_write = (commit_log_reg_t){((reg) << 1) | 1, wdata}; \
+    DO_WRITE_FREG(reg, wdata); \
+  })
 #endif
 
 // RVC macros
-#define WRITE_RVC_RDS(value) WRITE_REG(insn.rvc_rds(), value)
-#define WRITE_RVC_RS1S(value) WRITE_REG(insn.rvc_rs1s(), value)
 #define WRITE_RVC_RS2S(value) WRITE_REG(insn.rvc_rs2s(), value)
+#define WRITE_RVC_FRS2S(value) WRITE_FREG(insn.rvc_rs2s(), value)
 #define RVC_RS1 READ_REG(insn.rvc_rs1())
 #define RVC_RS2 READ_REG(insn.rvc_rs2())
 #define RVC_RS1S READ_REG(insn.rvc_rs1s())
 #define RVC_RS2S READ_REG(insn.rvc_rs2s())
+#define RVC_FRS2 STATE.FPR[insn.rvc_rs2()]
+#define RVC_FRS2S STATE.FPR[insn.rvc_rs2s()]
 #define RVC_SP READ_REG(X_SP)
 
 // FPU macros
@@ -150,17 +156,8 @@ private:
 #define FRS3 STATE.FPR[insn.rs3()]
 #define dirty_fp_state (STATE.mstatus |= MSTATUS_FS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
 #define dirty_ext_state (STATE.mstatus |= MSTATUS_XS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
-#define do_write_frd(value) (STATE.FPR.write(insn.rd(), value), dirty_fp_state)
- 
-#ifndef RISCV_ENABLE_COMMITLOG
-# define WRITE_FRD(value) do_write_frd(value)
-#else
-# define WRITE_FRD(value) ({ \
-        freg_t wdata = (value); /* value may have side effects */ \
-        STATE.log_reg_write = (commit_log_reg_t){(insn.rd() << 1) | 1, wdata}; \
-        do_write_frd(wdata); \
-      })
-#endif
+#define DO_WRITE_FREG(reg, value) (STATE.FPR.write(reg, value), dirty_fp_state)
+#define WRITE_FRD(value) WRITE_FREG(insn.rd(), value)
  
 #define SHAMT (insn.i_imm() & 0x3F)
 #define BRANCH_TARGET (pc + insn.sb_imm())