# error spike requires a two''s-complement c++ implementation
#endif
+#ifdef WORDS_BIGENDIAN
+# error spike requires a little-endian host
+#endif
+
#include <cstdint>
#include <string.h>
+#include <strings.h>
#include "encoding.h"
#include "config.h"
#include "common.h"
+#include "softfloat_types.h"
+#include "specialize.h"
#include <cinttypes>
typedef int64_t sreg_t;
typedef uint64_t reg_t;
-typedef uint64_t freg_t;
const int NXPR = 32;
const int NFPR = 32;
+const int NCSR = 4096;
+
+#define X_RA 1
+#define X_SP 2
#define FP_RD_NE 0
#define FP_RD_0 1
#define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
#define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
+#define insn_length(x) \
+ (((x) & 0x03) < 0x03 ? 2 : \
+ ((x) & 0x1f) < 0x1f ? 4 : \
+ ((x) & 0x3f) < 0x3f ? 6 : \
+ 8)
+#define MAX_INSN_LENGTH 8
+#define PC_ALIGN 2
+
+typedef uint64_t insn_bits_t;
class insn_t
{
public:
- uint32_t bits() { return b; }
- int32_t i_imm() { return int32_t(b) >> 20; }
- int32_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); }
- int32_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); }
- int32_t u_imm() { return int32_t(b) >> 12 << 12; }
- int32_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); }
- uint32_t rd() { return x(7, 5); }
- uint32_t rs1() { return x(15, 5); }
- uint32_t rs2() { return x(20, 5); }
- uint32_t rs3() { return x(27, 5); }
- uint32_t rm() { return x(12, 3); }
- uint32_t csr() { return x(20, 12); }
+ insn_t() = default;
+ insn_t(insn_bits_t bits) : b(bits) {}
+ insn_bits_t bits() { return b; }
+ int length() { return insn_length(b); }
+ int64_t i_imm() { return int64_t(b) >> 20; }
+ int64_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); }
+ int64_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); }
+ int64_t u_imm() { return int64_t(b) >> 12 << 12; }
+ int64_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); }
+ uint64_t rd() { return x(7, 5); }
+ uint64_t rs1() { return x(15, 5); }
+ uint64_t rs2() { return x(20, 5); }
+ uint64_t rs3() { return x(27, 5); }
+ uint64_t rm() { return x(12, 3); }
+ uint64_t csr() { return x(20, 12); }
+
+ int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); }
+ int64_t rvc_zimm() { return x(2, 5) + (x(12, 1) << 5); }
+ int64_t rvc_addi4spn_imm() { return (x(6, 1) << 2) + (x(5, 1) << 3) + (x(11, 2) << 4) + (x(7, 4) << 6); }
+ int64_t rvc_addi16sp_imm() { return (x(6, 1) << 4) + (x(2, 1) << 5) + (x(5, 1) << 6) + (x(3, 2) << 7) + (xs(12, 1) << 9); }
+ int64_t rvc_lwsp_imm() { return (x(4, 3) << 2) + (x(12, 1) << 5) + (x(2, 2) << 6); }
+ int64_t rvc_ldsp_imm() { return (x(5, 2) << 3) + (x(12, 1) << 5) + (x(2, 3) << 6); }
+ int64_t rvc_swsp_imm() { return (x(9, 4) << 2) + (x(7, 2) << 6); }
+ int64_t rvc_sdsp_imm() { return (x(10, 3) << 3) + (x(7, 3) << 6); }
+ int64_t rvc_lw_imm() { return (x(6, 1) << 2) + (x(10, 3) << 3) + (x(5, 1) << 6); }
+ int64_t rvc_ld_imm() { return (x(10, 3) << 3) + (x(5, 2) << 6); }
+ int64_t rvc_j_imm() { return (x(3, 3) << 1) + (x(11, 1) << 4) + (x(2, 1) << 5) + (x(7, 1) << 6) + (x(6, 1) << 7) + (x(9, 2) << 8) + (x(8, 1) << 10) + (xs(12, 1) << 11); }
+ int64_t rvc_b_imm() { return (x(3, 2) << 1) + (x(10, 2) << 3) + (x(2, 1) << 5) + (x(5, 2) << 6) + (xs(12, 1) << 8); }
+ int64_t rvc_simm3() { return x(10, 3); }
+ uint64_t rvc_rd() { return rd(); }
+ uint64_t rvc_rs1() { return rd(); }
+ uint64_t rvc_rs2() { return x(2, 5); }
+ uint64_t rvc_rs1s() { return 8 + x(7, 3); }
+ uint64_t rvc_rs2s() { return 8 + x(2, 3); }
private:
- uint32_t b;
- uint32_t x(int lo, int len) { return b << (32-lo-len) >> (32-len); }
- uint32_t xs(int lo, int len) { return int32_t(b) << (32-lo-len) >> (32-len); }
- uint32_t imm_sign() { return xs(31, 1); }
+ insn_bits_t b;
+ uint64_t x(int lo, int len) { return (b >> lo) & ((insn_bits_t(1) << len)-1); }
+ uint64_t xs(int lo, int len) { return int64_t(b) << (64-lo-len) >> (64-len); }
+ uint64_t imm_sign() { return xs(63, 1); }
};
template <class T, size_t N, bool zero_reg>
class regfile_t
{
public:
- void reset()
- {
- memset(data, 0, sizeof(data));
- }
void write(size_t i, T value)
{
- data[i] = value;
- if (zero_reg)
- data[0] = 0;
+ if (!zero_reg || i != 0)
+ data[i] = value;
}
const T& operator [] (size_t i) const
{
// helpful macros, etc
#define MMU (*p->get_mmu())
#define STATE (*p->get_state())
-#define RS1 STATE.XPR[insn.rs1()]
-#define RS2 STATE.XPR[insn.rs2()]
-#define WRITE_RD(value) STATE.XPR.write(insn.rd(), value)
-
-#ifdef RISCV_ENABLE_COMMITLOG
- #undef WRITE_RD
- #define WRITE_RD(value) ({ \
- reg_t wdata = value; /* value is a func with side-effects */ \
- STATE.log_reg_write = (commit_log_reg_t){insn.rd() << 1, wdata}; \
- STATE.XPR.write(insn.rd(), wdata); \
- })
-#endif
+#define READ_REG(reg) STATE.XPR[reg]
+#define READ_FREG(reg) STATE.FPR[reg]
+#define RS1 READ_REG(insn.rs1())
+#define RS2 READ_REG(insn.rs2())
+#define WRITE_RD(value) WRITE_REG(insn.rd(), value)
-#define FRS1 STATE.FPR[insn.rs1()]
-#define FRS2 STATE.FPR[insn.rs2()]
-#define FRS3 STATE.FPR[insn.rs3()]
-#define WRITE_FRD(value) STATE.FPR.write(insn.rd(), value)
-
-#ifdef RISCV_ENABLE_COMMITLOG
- #undef WRITE_FRD
- #define WRITE_FRD(value) ({ \
- freg_t wdata = value; /* value is a func with side-effects */ \
- STATE.log_reg_write = (commit_log_reg_t){(insn.rd() << 1) | 1, wdata}; \
- STATE.FPR.write(insn.rd(), wdata); \
- })
+#ifndef RISCV_ENABLE_COMMITLOG
+# define WRITE_REG(reg, value) STATE.XPR.write(reg, value)
+# define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, freg(value))
+#else
+# define WRITE_REG(reg, value) ({ \
+ reg_t wdata = (value); /* value may have side effects */ \
+ STATE.log_reg_write = (commit_log_reg_t){(reg) << 1, {wdata, 0}}; \
+ STATE.XPR.write(reg, wdata); \
+ })
+# define WRITE_FREG(reg, value) ({ \
+ freg_t wdata = freg(value); /* value may have side effects */ \
+ STATE.log_reg_write = (commit_log_reg_t){((reg) << 1) | 1, wdata}; \
+ DO_WRITE_FREG(reg, wdata); \
+ })
#endif
+
+// RVC macros
+#define WRITE_RVC_RS1S(value) WRITE_REG(insn.rvc_rs1s(), value)
+#define WRITE_RVC_RS2S(value) WRITE_REG(insn.rvc_rs2s(), value)
+#define WRITE_RVC_FRS2S(value) WRITE_FREG(insn.rvc_rs2s(), value)
+#define RVC_RS1 READ_REG(insn.rvc_rs1())
+#define RVC_RS2 READ_REG(insn.rvc_rs2())
+#define RVC_RS1S READ_REG(insn.rvc_rs1s())
+#define RVC_RS2S READ_REG(insn.rvc_rs2s())
+#define RVC_FRS2 READ_FREG(insn.rvc_rs2())
+#define RVC_FRS2S READ_FREG(insn.rvc_rs2s())
+#define RVC_SP READ_REG(X_SP)
+
+// FPU macros
+#define FRS1 READ_FREG(insn.rs1())
+#define FRS2 READ_FREG(insn.rs2())
+#define FRS3 READ_FREG(insn.rs3())
+#define dirty_fp_state (STATE.mstatus |= MSTATUS_FS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
+#define dirty_ext_state (STATE.mstatus |= MSTATUS_XS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
+#define DO_WRITE_FREG(reg, value) (STATE.FPR.write(reg, value), dirty_fp_state)
+#define WRITE_FRD(value) WRITE_FREG(insn.rd(), value)
#define SHAMT (insn.i_imm() & 0x3F)
#define BRANCH_TARGET (pc + insn.sb_imm())
#define JUMP_TARGET (pc + insn.uj_imm())
#define RM ({ int rm = insn.rm(); \
if(rm == 7) rm = STATE.frm; \
- if(rm > 4) throw trap_illegal_instruction(); \
+ if(rm > 4) throw trap_illegal_instruction(0); \
rm; })
-#define xpr64 (xprlen == 64)
+#define get_field(reg, mask) (((reg) & (decltype(reg))(mask)) / ((mask) & ~((mask) << 1)))
+#define set_field(reg, mask, val) (((reg) & ~(decltype(reg))(mask)) | (((decltype(reg))(val) * ((mask) & ~((mask) << 1))) & (decltype(reg))(mask)))
-#define require_supervisor if(unlikely(!(STATE.sr & SR_S))) throw trap_privileged_instruction()
-#define require_xpr64 if(unlikely(!xpr64)) throw trap_illegal_instruction()
-#define require_xpr32 if(unlikely(xpr64)) throw trap_illegal_instruction()
-#ifndef RISCV_ENABLE_FPU
-# define require_fp throw trap_illegal_instruction()
-#else
-# define require_fp if(unlikely(!(STATE.sr & SR_EF))) throw trap_fp_disabled()
-#endif
-#define require_accelerator if(unlikely(!(STATE.sr & SR_EA))) throw trap_accelerator_disabled()
+#define require(x) if (unlikely(!(x))) throw trap_illegal_instruction(0)
+#define require_privilege(p) require(STATE.prv >= (p))
+#define require_rv64 require(xlen == 64)
+#define require_rv32 require(xlen == 32)
+#define require_extension(s) require(p->supports_extension(s))
+#define require_fp require((STATE.mstatus & MSTATUS_FS) != 0)
+#define require_accelerator require((STATE.mstatus & MSTATUS_XS) != 0)
-#define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
-#define set_fp_exceptions ({ STATE.fflags |= softfloat_exceptionFlags; \
+#define set_fp_exceptions ({ if (softfloat_exceptionFlags) { \
+ dirty_fp_state; \
+ STATE.fflags |= softfloat_exceptionFlags; \
+ } \
softfloat_exceptionFlags = 0; })
#define sext32(x) ((sreg_t)(int32_t)(x))
#define zext32(x) ((reg_t)(uint32_t)(x))
-#define sext_xprlen(x) (((sreg_t)(x) << (64-xprlen)) >> (64-xprlen))
-#define zext_xprlen(x) (((reg_t)(x) << (64-xprlen)) >> (64-xprlen))
-
-#define insn_length(x) \
- (((x) & 0x03) < 0x03 ? 2 : \
- ((x) & 0x1f) < 0x1f ? 4 : \
- ((x) & 0x3f) < 0x3f ? 6 : \
- 8)
+#define sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen))
+#define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))
#define set_pc(x) \
- do { if ((x) & 3 /* For now... */) \
- throw trap_instruction_address_misaligned(); \
- npc = sext_xprlen(x); \
+ do { p->check_pc_alignment(x); \
+ npc = sext_xlen(x); \
+ } while(0)
+
+#define set_pc_and_serialize(x) \
+ do { reg_t __npc = (x); \
+ npc = PC_SERIALIZE_AFTER; \
+ STATE.pc = __npc; \
} while(0)
+#define serialize() set_pc_and_serialize(npc)
+
+/* Sentinel PC values to serialize simulator pipeline */
+#define PC_SERIALIZE_BEFORE 3
+#define PC_SERIALIZE_AFTER 5
+#define invalid_pc(pc) ((pc) & 1)
+
+/* Convenience wrappers to simplify softfloat code sequences */
+#define isBoxedF32(r) (isBoxedF64(r) && ((uint32_t)((r.v[0] >> 32) + 1) == 0))
+#define unboxF32(r) (isBoxedF32(r) ? (uint32_t)r.v[0] : defaultNaNF32UI)
+#define isBoxedF64(r) ((r.v[1] + 1) == 0)
+#define unboxF64(r) (isBoxedF64(r) ? r.v[0] : defaultNaNF64UI)
+typedef float128_t freg_t;
+inline float32_t f32(uint32_t v) { return { v }; }
+inline float64_t f64(uint64_t v) { return { v }; }
+inline float32_t f32(freg_t r) { return f32(unboxF32(r)); }
+inline float64_t f64(freg_t r) { return f64(unboxF64(r)); }
+inline float128_t f128(freg_t r) { return r; }
+inline freg_t freg(float32_t f) { return { ((uint64_t)-1 << 32) | f.v, (uint64_t)-1 }; }
+inline freg_t freg(float64_t f) { return { f.v, (uint64_t)-1 }; }
+inline freg_t freg(float128_t f) { return f; }
+#define F32_SIGN ((uint32_t)1 << 31)
+#define F64_SIGN ((uint64_t)1 << 63)
+#define fsgnj32(a, b, n, x) \
+ f32((f32(a).v & ~F32_SIGN) | ((((x) ? f32(a).v : (n) ? F32_SIGN : 0) ^ f32(b).v) & F32_SIGN))
+#define fsgnj64(a, b, n, x) \
+ f64((f64(a).v & ~F64_SIGN) | ((((x) ? f64(a).v : (n) ? F64_SIGN : 0) ^ f64(b).v) & F64_SIGN))
+
+#define isNaNF128(x) isNaNF128UI(x.v[1], x.v[0])
+inline float128_t defaultNaNF128()
+{
+ float128_t nan;
+ nan.v[1] = defaultNaNF128UI64;
+ nan.v[0] = defaultNaNF128UI0;
+ return nan;
+}
+inline freg_t fsgnj128(freg_t a, freg_t b, bool n, bool x)
+{
+ a.v[1] = (a.v[1] & ~F64_SIGN) | (((x ? a.v[1] : n ? F64_SIGN : 0) ^ b.v[1]) & F64_SIGN);
+ return a;
+}
+inline freg_t f128_negate(freg_t a)
+{
+ a.v[1] ^= F64_SIGN;
+ return a;
+}
+
#define validate_csr(which, write) ({ \
- unsigned my_priv = (STATE.sr & SR_S) ? 1 : 0; \
- unsigned read_priv = ((which) >> 10) & 3; \
- unsigned write_priv = (((which) >> 8) & 3); \
- if (read_priv == 3) read_priv = write_priv, write_priv = -1; \
- if (my_priv < ((write) ? write_priv : read_priv)) \
- throw trap_privileged_instruction(); \
+ if (!STATE.serialized) return PC_SERIALIZE_BEFORE; \
+ STATE.serialized = false; \
+ unsigned csr_priv = get_field((which), 0x300); \
+ unsigned csr_read_only = get_field((which), 0xC00) == 3; \
+ if (((write) && csr_read_only) || STATE.prv < csr_priv) \
+ throw trap_illegal_instruction(0); \
(which); })
+// Seems that 0x0 doesn't work.
+#define DEBUG_START 0x100
+#define DEBUG_END (0x1000 - 1)
+
#endif
projects / riscv-isa-sim.git / blobdiff