Merge remote-tracking branch 'origin/priv-1.10' into HEAD

[riscv-isa-sim.git] / riscv / decode.h

diff --git a/riscv/decode.h b/riscv/decode.h
index c3487b103a25906575d2806f3646f2fe6da203bb..7667b273a7339af4a3d23413a807062b901779aa 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -246,17 +246,19 @@ inline freg_t freg(freg_t f) { return f; }
     throw trap_illegal_instruction(0); \
   (which); })
 
-#define DEBUG_START             0x100
-#define DEBUG_ROM_START         0x800
-#define DEBUG_ROM_RESUME        (DEBUG_ROM_START + 4)
-#define DEBUG_ROM_EXCEPTION     (DEBUG_ROM_START + 8)
-#define DEBUG_ROM_END           (DEBUG_ROM_START + debug_rom_raw_len)
-#define DEBUG_RAM_START         0x400
+#define DEBUG_START             0x20000
+#define DEBUG_ROM_ENTRY         DEBUG_START
+#define DEBUG_ROM_ENTRY_SIZE    (1024 * 4)
+#define DEBUG_ROM_CODE          (DEBUG_ROM_ENTRY + DEBUG_ROM_ENTRY_SIZE)
+#define DEBUG_ROM_CODE_SIZE     256
+#define DEBUG_ROM_EXCEPTION     (DEBUG_ROM_CODE + DEBUG_ROM_CODE_SIZE)
+#define DEBUG_ROM_EXCEPTION_SIZE        4
+#define DEBUG_RAM_START         (DEBUG_ROM_EXCEPTION + DEBUG_ROM_EXCEPTION_SIZE)
 #define DEBUG_RAM_SIZE          64
 #define DEBUG_RAM_END           (DEBUG_RAM_START + DEBUG_RAM_SIZE)
-#define DEBUG_END               0xfff
-#define DEBUG_CLEARDEBINT       0x100
-#define DEBUG_SETHALTNOT        0x10c
-#define DEBUG_SIZE              (DEBUG_END - DEBUG_START + 1)
+#define DEBUG_END               DEBUG_RAM_END
+
+#define DEBUG_EXCHANGE          0x400
+#define DEBUG_EXCHANGE_SIZE     0x20
 
 #endif