#else
# define WRITE_REG(reg, value) ({ \
reg_t wdata = (value); /* value may have side effects */ \
- STATE.log_reg_write = (commit_log_reg_t){(reg) << 1, wdata}; \
+ STATE.log_reg_write = (commit_log_reg_t){(reg) << 1, {wdata, 0}}; \
STATE.XPR.write(reg, wdata); \
})
# define WRITE_FREG(reg, value) ({ \
freg_t wdata = freg(value); /* value may have side effects */ \
- STATE.log_reg_write = (commit_log_reg_t){((reg) << 1) | 1, wdata.v}; \
+ STATE.log_reg_write = (commit_log_reg_t){((reg) << 1) | 1, wdata}; \
DO_WRITE_FREG(reg, wdata); \
})
#endif
#define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))
#define set_pc(x) \
- do { if (unlikely(((x) & 2)) && !p->supports_extension('C')) \
- throw trap_instruction_address_misaligned(x); \
+ do { p->check_pc_alignment(x); \
npc = sext_xlen(x); \
} while(0)
#define set_pc_and_serialize(x) \
- do { reg_t __npc = (x); \
- set_pc(__npc); /* check alignment */ \
+ do { reg_t __npc = (x) & p->pc_alignment_mask(); \
npc = PC_SERIALIZE_AFTER; \
STATE.pc = __npc; \
} while(0)
+#define serialize() set_pc_and_serialize(npc)
+
/* Sentinel PC values to serialize simulator pipeline */
#define PC_SERIALIZE_BEFORE 3
#define PC_SERIALIZE_AFTER 5