Implement RVC draft

[riscv-isa-sim.git] / riscv / decode.h

diff --git a/riscv/decode.h b/riscv/decode.h
index 72efcd9e9464ffef1d92ec4e9270c504e9f32515..a1c28d50827d6a0a0a888c84595bc4dff77a6ad8 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -45,6 +45,14 @@ const int NFPR = 32;
 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
 
+#ifdef RISCV_ENABLE_RVC
+# define INSN_ALIGNMENT 2
+# define require_rvc
+#else
+# define INSN_ALIGNMENT 4
+# define require_rvc throw trap_illegal_instruction()
+#endif
+
 #define insn_length(x) \
   (((x) & 0x03) < 0x03 ? 2 : \
    ((x) & 0x1f) < 0x1f ? 4 : \
@@ -70,6 +78,20 @@ public:
   uint64_t rs3() { return x(27, 5); }
   uint64_t rm() { return x(12, 3); }
   uint64_t csr() { return x(20, 12); }
+
+  int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); }
+  int64_t rvc_lwsp_imm() { return (x(4, 3) << 2) + (x(12, 1) << 5) + (x(2, 2) << 6); }
+  int64_t rvc_ldsp_imm() { return (x(5, 2) << 3) + (x(12, 1) << 5) + (x(2, 3) << 6); }
+  int64_t rvc_lw_imm() { return (x(5, 2) << 3) + (x(10, 1) << 6) + (x(11, 1) << 2) + (x(12, 1) << 5); }
+  int64_t rvc_ld_imm() { return (x(5, 2) << 3) + (x(10, 1) << 6) + (x(11, 1) << 7) + (x(12, 1) << 5); }
+  int64_t rvc_j_imm() { return (xs(2, 3) << 9) + (x(5, 2) << 3) + (x(7, 1) << 1) + (x(8, 2) << 7) + (x(10, 1) << 6) + (x(11, 1) << 2) + (x(12, 1) << 5); }
+  int64_t rvc_b_imm() { return (x(5, 2) << 3) + (x(7, 1) << 1) + (xs(8, 2) << 7) + (x(10, 1) << 6) + (x(11, 1) << 2) + (x(12, 1) << 5); }
+  uint64_t rvc_rd() { return rd(); }
+  uint64_t rvc_rs1() { return x(2, 5); }
+  uint64_t rvc_rs2() { return rd(); }
+  uint64_t rvc_rds() { return 8 + x(7, 3); }
+  uint64_t rvc_rs1s() { return 8 + x(2, 3); }
+  uint64_t rvc_rs2s() { return rvc_rds(); }
 private:
   insn_bits_t b;
   uint64_t x(int lo, int len) { return (b >> lo) & ((insn_bits_t(1) << len)-1); }
@@ -99,17 +121,27 @@ private:
 #define STATE (*p->get_state())
 #define RS1 STATE.XPR[insn.rs1()]
 #define RS2 STATE.XPR[insn.rs2()]
-#define WRITE_RD(value) STATE.XPR.write(insn.rd(), value)
+#define WRITE_REG(reg, value) STATE.XPR.write(reg, value)
+#define WRITE_RD(value) WRITE_REG(insn.rd(), value)
 
 #ifdef RISCV_ENABLE_COMMITLOG
-  #undef WRITE_RD 
-  #define WRITE_RD(value) ({ \
+  #undef WRITE_REG
+  #define WRITE_REG(reg, value) ({ \
         reg_t wdata = value; /* value is a func with side-effects */ \
-        STATE.log_reg_write = (commit_log_reg_t){insn.rd() << 1, wdata}; \
-        STATE.XPR.write(insn.rd(), wdata); \
+        STATE.log_reg_write = (commit_log_reg_t){reg << 1, wdata}; \
+        STATE.XPR.write(reg, wdata); \
       })
 #endif
 
+// RVC macros
+#define WRITE_RVC_RDS(value) WRITE_REG(insn.rvc_rds(), value)
+#define RVC_RS1 STATE.XPR[insn.rvc_rs1()]
+#define RVC_RS2 STATE.XPR[insn.rvc_rs2()]
+#define RVC_RS1S STATE.XPR[insn.rvc_rs1s()]
+#define RVC_RS2S STATE.XPR[insn.rvc_rs2s()]
+#define RVC_SP STATE.XPR[2]
+
+// FPU macros
 #define FRS1 STATE.FPR[insn.rs1()]
 #define FRS2 STATE.FPR[insn.rs2()]
 #define FRS3 STATE.FPR[insn.rs3()]
@@ -154,7 +186,7 @@ private:
 #define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))
 
 #define set_pc(x) \
-  do { if ((x) & 3 /* For now... */) \
+  do { if ((x) & (INSN_ALIGNMENT-1)) \
          throw trap_instruction_address_misaligned(x); \
        npc = sext_xlen(x); \
      } while(0)