Commit log now prints while interrupts are enabled.

[riscv-isa-sim.git] / riscv / decode.h

diff --git a/riscv/decode.h b/riscv/decode.h
index 4c3d274b613f0036af5f9b7644d82a0a19f45a82..ce57c772ffbf4c6073d52dda056098bf31ab9598 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -101,10 +101,8 @@ private:
 #ifdef RISCV_ENABLE_COMMITLOG
   #undef WRITE_RD 
   #define WRITE_RD(value) ({ \
-        bool in_spvr = p->get_state()->sr & SR_S; \
         reg_t wdata = value; /* value is a func with side-effects */ \
-        if (!in_spvr) \
-          p->get_state()->log_reg_write = (commit_log_reg_t){insn.rd() << 1, wdata}; \
+        p->get_state()->log_reg_write = (commit_log_reg_t){insn.rd() << 1, wdata}; \
         p->get_state()->XPR.write(insn.rd(), wdata); \
       })
 #endif
@@ -117,10 +115,8 @@ private:
 #ifdef RISCV_ENABLE_COMMITLOG
   #undef WRITE_FRD 
   #define WRITE_FRD(value) ({ \
-        bool in_spvr = p->get_state()->sr & SR_S; \
         freg_t wdata = value; /* value is a func with side-effects */ \
-        if (!in_spvr) \
-          p->get_state()->log_reg_write = (commit_log_reg_t){(insn.rd() << 1) | 1, wdata}; \
+        p->get_state()->log_reg_write = (commit_log_reg_t){(insn.rd() << 1) | 1, wdata}; \
         p->get_state()->FPR.write(insn.rd(), wdata); \
       })
 #endif