Merge remote-tracking branch 'origin/priv-1.10' into HEAD

[riscv-isa-sim.git] / riscv / execute.cc

diff --git a/riscv/execute.cc b/riscv/execute.cc
index 0ac0e0ac43c729cfa08f5c6a7b3dd079b1f2177e..7734ca2749d6756ca2270e6c359a3d28db712ec9 100644 (file)
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -79,7 +79,7 @@ void processor_t::step(size_t n)
      if (unlikely(invalid_pc(pc))) { \
        switch (pc) { \
          case PC_SERIALIZE_BEFORE: state.serialized = true; break; \
-         case PC_SERIALIZE_AFTER: instret++; break; \
+         case PC_SERIALIZE_AFTER: n = ++instret; break; \
          default: abort(); \
        } \
        pc = state.pc; \
@@ -91,7 +91,7 @@ void processor_t::step(size_t n)
 
     try
     {
-      take_interrupt();
+      take_pending_interrupt();
 
       if (unlikely(slow_path()))
       {