#include "processor.h"
#include "mmu.h"
-#include "sim.h"
#include <cassert>
{
while (instret < n)
{
+ if (unlikely(!state.serialized && state.single_step == state.STEP_STEPPED)) {
+ state.single_step = state.STEP_NONE;
+ enter_debug_mode(DCSR_CAUSE_STEP);
+ // enter_debug_mode changed state.pc, so we can't just continue.
+ break;
+ }
+
if (unlikely(state.single_step == state.STEP_STEPPING)) {
state.single_step = state.STEP_STEPPED;
}
if (debug && !state.serialized)
disasm(fetch.insn);
pc = execute_insn(this, pc, fetch);
- bool serialize_before = (pc == PC_SERIALIZE_BEFORE);
advance_pc();
- if (unlikely(state.single_step == state.STEP_STEPPED) && !serialize_before) {
- state.single_step = state.STEP_NONE;
- enter_debug_mode(DCSR_CAUSE_STEP);
- // enter_debug_mode changed state.pc, so we can't just continue.
- break;
- }
-
- if (unlikely(state.pc >= DEBUG_START &&
+ if (unlikely(state.pc >= DEBUG_ROM_ENTRY &&
state.pc < DEBUG_END)) {
// We're waiting for the debugger to tell us something.
return;
}
-
-
}
}
else while (instret < n)
//
// According to Andrew Waterman's recollection, this optimization
// resulted in approximately a 2x performance increase.
- //
- // If there is support for compressed instructions, the mmu and the
- // switch statement get more complicated. Each branch target is stored
- // in the index corresponding to mmu->icache_index(), but consecutive
- // non-branching instructions are stored in consecutive indices even if
- // mmu->icache_index() specifies a different index (which is the case
- // for 32-bit instructions in the presence of compressed instructions).
// This figures out where to jump to in the switch statement
size_t idx = _mmu->icache_index(pc);
// is located within the execute_insn() function call.
#define ICACHE_ACCESS(i) { \
insn_fetch_t fetch = ic_entry->data; \
- ic_entry++; \
pc = execute_insn(this, pc, fetch); \
+ ic_entry = ic_entry->next; \
if (i == mmu_t::ICACHE_ENTRIES-1) break; \
- if (unlikely(ic_entry->tag != pc)) goto miss; \
+ if (unlikely(ic_entry->tag != pc)) break; \
if (unlikely(instret+1 == n)) break; \
instret++; \
state.pc = pc; \
}
advance_pc();
- continue;
-
-miss:
- advance_pc();
- // refill I$ if it looks like there wasn't a taken branch
- if (pc > (ic_entry-1)->tag && pc <= (ic_entry-1)->tag + MAX_INSN_LENGTH)
- _mmu->refill_icache(pc, ic_entry);
}
}
catch(trap_t& t)