Implement Hauser misa.C misalignment proposal (#187)

[riscv-isa-sim.git] / riscv / execute.cc

diff --git a/riscv/execute.cc b/riscv/execute.cc
index f8f122ad2a33a758b60cbe0c69bf0a7504f9d3c6..9d1fb87ad2da6a8cccca13eb3f01e5ff61147ac4 100644 (file)
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -113,7 +113,6 @@ void processor_t::step(size_t n)
          default: abort(); \
        } \
        pc = state.pc; \
-       check_pc_alignment(pc); \
        break; \
      } else { \
        state.pc = pc; \
@@ -128,6 +127,13 @@ void processor_t::step(size_t n)
       {
         while (instret < n)
         {
+          if (unlikely(!state.serialized && state.single_step == state.STEP_STEPPED)) {
+            state.single_step = state.STEP_NONE;
+            enter_debug_mode(DCSR_CAUSE_STEP);
+            // enter_debug_mode changed state.pc, so we can't just continue.
+            break;
+          }
+
           if (unlikely(state.single_step == state.STEP_STEPPING)) {
             state.single_step = state.STEP_STEPPED;
           }
@@ -136,17 +142,9 @@ void processor_t::step(size_t n)
           if (debug && !state.serialized)
             disasm(fetch.insn);
           pc = execute_insn(this, pc, fetch);
-          bool serialize_before = (pc == PC_SERIALIZE_BEFORE);
 
           advance_pc();
 
-          if (unlikely(state.single_step == state.STEP_STEPPED) && !serialize_before) {
-            state.single_step = state.STEP_NONE;
-            enter_debug_mode(DCSR_CAUSE_STEP);
-            // enter_debug_mode changed state.pc, so we can't just continue.
-            break;
-          }
-
           if (unlikely(state.pc >= DEBUG_ROM_ENTRY &&
                        state.pc < DEBUG_END)) {
             // We're waiting for the debugger to tell us something.