Move towards RVC v1.8

[riscv-isa-sim.git] / riscv / insns / c_add.h

diff --git a/riscv/insns/c_add.h b/riscv/insns/c_add.h
index 64bc5f7578cc701393dd1f711a0a06583f708850..c13385ec4dec0bf471daaeb64f6bdb15b07bfcbf 100644 (file)
--- a/riscv/insns/c_add.h
+++ b/riscv/insns/c_add.h
@@ -1,7 +1,12 @@
 require_extension('C');
-require(insn.rvc_rs2() != 0);
-if (insn.rvc_rd() == 0) { // c.ebreak
-  throw trap_breakpoint();
+if (insn.rvc_rs2() == 0) {
+  if (insn.rvc_rs1() == 0) { // c.ebreak
+    throw trap_breakpoint();
+  } else { // c.jalr
+    reg_t tmp = npc;
+    set_pc(RVC_RS1 & ~reg_t(1));
+    WRITE_REG(X_RA, tmp);
+  }
 } else {
   WRITE_RD(sext_xlen(RVC_RS1 + RVC_RS2));
 }