work towards rvc 1.8

[riscv-isa-sim.git] / riscv / insns / c_addw.h

diff --git a/riscv/insns/c_addw.h b/riscv/insns/c_addw.h
index fef554d1f62ed7cce7e27b7ad5c2f220e667c98c..6e0ae3a52c2dab09dbe545d357b50fae493457f8 100644 (file)
--- a/riscv/insns/c_addw.h
+++ b/riscv/insns/c_addw.h
@@ -1,3 +1,3 @@
 require_extension('C');
 require_rv64;
-WRITE_RD(sext32(RVC_RS1 + RVC_RS2));
+WRITE_RVC_RS1S(sext32(RVC_RS1S + RVC_RS2S));